Lptim Control Register (Lptimx_Cr) - ST STM32L4x6 Reference Manual

RM0351
30.7.5

LPTIM control register (LPTIMx_CR)

Address offset: 0x10
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 CNTSTRT: Timer start in Continuous mode
This bit is set by software and cleared by hardware.
In case of software start (TRIGEN[1:0] = '00'), setting this bit starts the LPTIM in Continuous mode.
If the software start is disabled (TRIGEN[1:0] different than '00'), setting this bit starts the timer in
Continuous mode as soon as an external trigger is detected.
If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next
match between the LPTIMx_ARR and LPTIMx_CNT registers and the LPTIM counter keeps
counting in Continuous mode.
This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware.
Bit 1 SNGSTRT: LPTIM start in Single mode
This bit is set by software and cleared by hardware.
In case of software start (TRIGEN[1:0] = '00'), setting this bit starts the LPTIM in single pulse mode.
If the software start is disabled (TRIGEN[1:0] different than '00'), setting this bit starts the LPTIM in
single pulse mode as soon as an external trigger is detected.
If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the
following match between LPTIMx_ARR and LPTIMx_CNT registers.
This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware.
Bit 0 ENABLE: LPTIM enable
The ENABLE bit is set and cleared by software.
0:LPTIM is disabled
1:LPTIM is enabled
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
DocID024597 Rev 3
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res. Res. Res. Res.
Low-power timer (LPTIM)
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
CNT SNG
Res. Res.
STRT STRT
rw rw
1041/1693
16
Res.
0
ENA
BLE
rw
1045