ST STM32L4x6 Reference Manual page 683

RM0351
Bits 31:26 Reserved, must be kept at reset value
Bits 25:22 PS[3:0]: PS 16-bit prescaler
These bits are written by software to define the division factor of the PS 16-bit prescaler.
ck_ps = LCDCLK/(2). See
1111:ck_ps = LCDCLK/32768
Bits 21:18 DIV[3:0]: DIV clock divider
These bits are written by software to define the division factor of the DIV divider. See
Section
1111:ck_div = ck_ps/31
Bits 17:16 BLINK[1:0]: Blink mode selection
Bits 15:13 BLINKF[2:0]: Blink frequency selection
Bits 12:10 CC[2:0]: Contrast control
These bits specify one of the V
2.60 V to 3.51V.
Refer to the product datasheet for the V
0000: ck_ps = LCDCLK
0001: ck_ps = LCDCLK/2
0002: ck_ps = LCDCLK/4
...
22.3.2.
0000: ck_div = ck_ps/16
0001: ck_div = ck_ps/17
0002: ck_div = ck_ps/18
...
00: Blink disabled
01: Blink enabled on SEG[0], COM[0] (1 pixel)
10: Blink enabled on SEG[0], all COMs (up to 8 pixels depending on the programmed duty)
11: Blink enabled on all SEGs and all COMs (all pixels)
000: f /8
LCD
001: f /16
LCD
010: f /32
LCD
011: f /64
LCD
100: f /128
LCD
101: f /256
LCD
110: f /512
LCD
111: f /1024
LCD
000: V
LCD0
001: V
LCD1
010: V
LCD2
011: V
LCD3
100: V
LCD4
101: V
LCD5
110: V
LCD6
111: V
LCD7
DocID024597 Rev 3
Liquid crystal display controller (LCD)
Section 22.3.2.
maximum voltages (independent of V
LCD
values.
LCDx
). It ranges from
DD
683/1693
690