Table 56. Fmc_Bcrx Bit Fields; Figure 32. Mode1 Write Access Waveforms - ST STM32L4x6 Reference Manual

RM0351
The one HCLK cycle at the end of the write transaction helps guarantee the address and
data hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the
DATAST value must be greater than zero (DATAST > 0).
Bit number
31-21
20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4

Figure 32. Mode1 write access waveforms

Table 56. FMC_BCRx bit fields

Bit name
Reserved 0x000
CCLKEN As needed
CBURSTRW 0x0 (no effect in asynchronous mode)
CPSIZE 0x0 (no effect in asynchronous mode)
ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
EXTMOD 0x0
WAITEN 0x0 (no effect in asynchronous mode)
WREN As needed
Reserved 0x0
WRAPMOD 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
FACCEN Don't care
MWID As needed
DocID024597 Rev 3
Flexible static memory controller (FSMC)
Value to set
355/1693
399