Sram2 Read Protection; Sram2 Erase; Flash Memory Overview - ST STM32L4x6 Reference Manual

The write protection can be enabled in
(SYSCFG_SWPR)
which means by writing '1' on a bit it will setup the write protection for that page of SRAM
and it can be removed/cleared by a system reset only.
2.4.3

SRAM2 Read protection

The SRAM2 is protected with the Read protection (RDP). Refer to
protection (RDP)
2.4.4

SRAM2 Erase

The SRAM2 can be erased with a system reset using the option bit SRAM2_RST in the user
option byte (refer to
The SRAM2 erase can also be requested by software by setting the bit SRAM2ER in the
SYSCFG SRAM2 control and status register
2.5

Flash memory overview

The Flash memory is composed of two distinct physical areas:
•
The main Flash memory block. It contains the application program and user data if
necessary.
•
The information block. It is composed of three parts:
–
–
–
The Flash interface implements instruction access and data access based on the AHB
protocol. It implements a system of instruction prefetch and caches lines that speeds up
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Table 2. SRAM2 organization (continued)
Page number
Page 20
Page 21
Page 22
Page 23
Page 24
Page 25
Page 26
Page 27
Page 28
Page 29
Page 30
Page 31
in the SYSCFG block. This is a register with write '1' once mechanism,
for more details.
Section 3.4.1: Option bytes
Option bytes for hardware and memory protection user configuration.
System memory which contains the proprietary boot loader code.
OTP (one-time programmable) area
DocID024597 Rev 3
Start address
0x1000 5000
0x1000 5400
0x1000 5800
0x1000 5C00
0x1000 6000
0x1000 6400
0x1000 6800
0x1000 6C00
0x1000 7000
0x1000 7400
0x1000 7800
0x1000 7C00
SYSCFG SRAM2 write protection register
description).
(SYSCFG_SCSR).
RM0351
End address
0x1000 53FF
0x1000 57FF
0x1000 5BFF
0x1000 5FFF
0x1000 63FF
0x1000 67FF
0x1000 6BFF
0x1000 6FFF
0x1000 73FF
0x1000 77FF
0x1000 7BFF
0x1000 7FFF
Section 3.5.1: Read