Lcd Status Register (Lcd_Sr) - ST STM32L4x6 Reference Manual

Liquid crystal display controller (LCD)
22.6.3

LCD status register (LCD_SR)

Address offset: 0x08
Reset value: 0x0000 0020
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:6 Reserved, must be kept at reset value
Bit 5 FCRSF: LCD Frame Control Register Synchronization flag
This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK
domain. It is cleared by hardware when writing to the LCD_FCR register.
Bit 4 RDY: Ready flag
This bit is set and cleared by hardware. It indicates the status of the step-up converter.
Bit 3 UDD: Update Display Done
This bit is set by hardware. It is cleared by writing 1 to the UDDC bit in the LCD_CLR register.
The bit set has priority over the clear.
Note: If the device is in Stop mode (PCLK not provided) UDD will not generate an interrupt
686/1693
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
0: LCD Frame Control Register not yet synchronized
1: LCD Frame Control Register synchronized
0: Not ready
1: Step-up converter is enabled and ready to provide the correct voltage.
0: No event
1: Update Display Request done. A UDD interrupt is generated if the UDDIE bit in the
LCD_FCR register is set.
even if UDDIE = 1.
If the display is not enabled the UDD interrupt will never occur.
DocID024597 Rev 3
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res. Res. Res.
FCRSF
r
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
RDY UDD UDR SOF
r r rs r
RM0351
16
Res.
0
ENS
r