Tim1/Tim8 Counter (Timx_Cnt) - ST STM32L4x6 Reference Manual

RM0351
26.4.10

TIM1/TIM8 counter (TIMx_CNT)

Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
UIFCPY Res. Res.
r
15 14 13
rw rw rw
Bit 31 UIFCPY: UIF copy
This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the
TIMxCR1 is reset, bit 31 is reserved and read at 0.
Bits 30:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value
26.4.11 TIM1/TIM8 prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 PSC[15:0]: Prescaler value
The counter clock frequency (CK_CNT) is equal to f
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through trigger
controller when configured in "reset mode").
26.4.12 TIM1/TIM8 auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0xFFFF
15 14 13
rw rw rw
Bits 15:0 ARR[15:0]: Prescaler value
ARR is the value to be loaded in the actual auto-reload register.
Refer to the
and behavior.
The counter is blocked while the auto-reload value is null.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
rw rw rw rw
12 11 10 9
rw rw rw rw
12 11 10 9
rw rw rw rw
Section 26.3.1: Time-base unit on page 754
DocID024597 Rev 3
Advanced-control timers (TIM1/TIM8)
24 23 22 21
Res. Re s. Res. Res.
8 7 6 5
CNT[15:0]
rw rw rw rw
8 7 6 5
PSC[15:0]
rw rw rw rw
CK_PSC
8 7 6 5
ARR[15:0]
rw rw rw rw
20
19 18
Res. Res. Res.
4 3 2
rw rw rw
4 3 2
rw rw rw
/ (PSC[15:0] + 1).
4 3 2
rw rw rw
for more details about ARR update
17 16
Res. Res.
1 0
rw rw
1 0
rw rw
1 0
rw rw
833/1693
856