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STM32F207 series
ST STM32F207 series Manuals
Manuals and User Guides for ST STM32F207 series. We have
3
ST STM32F207 series manuals available for free PDF download: Reference Manual, Programming Manual
ST STM32F207 series Reference Manual (1378 pages)
advanced Arm-based 32-bit MCUs
Brand:
ST
| Category:
Microcontrollers
| Size: 17 MB
Table of Contents
Table of Contents
2
SYSCFG External Interrupt Configuration Register
4
Documentation Conventions
46
General Information
46
List of Abbreviations for Registers
46
Glossary
46
Peripheral Availability
47
Memory and Bus Architecture
48
System Architecture
48
S0: I-Bus
49
S1: D-Bus
49
S2: S-Bus
49
S3, S4: DMA Memory Bus
49
Figure 1. System Architecture
49
S5: DMA Peripheral Bus
50
S6: Ethernet DMA Bus
50
S7: USB OTG HS DMA Bus
50
Busmatrix
50
AHB/APB Bridges (APB)
50
Memory Organization
50
Memory Map
51
Table 1. Stm32F20X and Stm32F21X Register Boundary Addresses
51
Embedded SRAM
53
Bit Banding
54
Embedded Flash Memory
55
Flash Memory Read Interface
55
Table 2. Flash Module Organization
55
Table 3. Number of Wait States According to Cortex ® -M3 Clock Frequency
56
Adaptive Real-Time Memory Accelerator (ART Accelerator™)
58
Boot Configuration
58
Table 4. Boot Modes
58
Table 5. Memory Mapping Vs. Boot Mode/Physical Remap
59
CRC Calculation Unit
61
CRC Introduction
61
CRC Main Features
61
Figure 2. CRC Calculation Unit Block Diagram
61
CRC Functional Description
62
CRC Registers
62
Data Register (CRC_DR)
62
Independent Data Register (CRC_IDR)
62
Control Register (CRC_CR)
63
CRC Register Map
63
Table 6. CRC Calculation Unit Register Map and Reset Values
63
Power Control (PWR)
64
Power Supplies
64
Figure 3. Power Supply Overview
64
Battery Backup Domain
65
Independent A/D Converter Supply and Reference Voltage
65
Table 17. RTC_AF2 Pin
66
Figure 4. Backup SRAM
67
Voltage Regulator
67
Power Supply Supervisor
68
Power-On Reset (Por)/Power-Down Reset (PDR)
68
Figure 5. Power-On/Power-Down Reset Waveform
68
Brownout Reset (BOR)
69
Programmable Voltage Detector (PVD)
69
Figure 6. BOR Thresholds
69
Low-Power Modes
70
Figure 7. PVD Thresholds
70
Peripheral Clock Gating
72
Slowing down System Clocks
72
Table 7. Low-Power Mode Summary
72
Sleep Mode
73
Table 8. Sleep-Now
73
Table 9. Sleep-On-Exit
73
Stop Mode
74
Table 10. Stop Mode
75
Standby Mode
76
Table 11. Standby Mode
77
Table 16. RTC_AF1 Pin
77
Programming the RTC Alternate Functions to Wake up the Device from the Stop and Standby Modes
78
Power Control Registers
80
PWR Power Control Register (PWR_CR)
80
PWR Power Control/Status Register (PWR_CSR)
81
PWR Register Map
83
Table 12. PWR - Register Map and Reset Values
83
Reset and Clock Control (RCC)
84
Reset
84
System Reset
84
Power Reset
85
Figure 8. Simplified Diagram of the Reset Circuit
85
Backup Domain Reset
86
Clocks
86
Figure 9. Clock Tree
87
HSE Clock
88
Figure 10. HSE/ LSE Clock Sources
89
HSI Clock
89
LSE Clock
90
PLL Configuration
90
Clock Security System (CSS)
91
LSI Clock
91
System Clock (SYSCLK) Selection
91
RTC/AWU Clock
92
Watchdog Clock
92
Clock-Out Capability
93
Internal/External Clock Measurement Using TIM5/TIM11
93
Figure 11. Frequency Measurement with TIM5 in Input Capture Mode
94
Figure 12. Frequency Measurement with TIM11 in Input Capture Mode
94
RCC Registers
95
RCC Clock Control Register (RCC_CR)
95
RCC PLL Configuration Register (RCC_PLLCFGR)
97
RCC Clock Configuration Register (RCC_CFGR)
99
RCC Clock Interrupt Register (RCC_CIR)
101
RCC AHB1 Peripheral Reset Register (RCC_AHB1RSTR)
104
RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR)
106
RCC AHB3 Peripheral Reset Register (RCC_AHB3RSTR)
107
RCC APB1 Peripheral Reset Register (RCC_APB1RSTR)
107
RCC APB2 Peripheral Reset Register (RCC_APB2RSTR)
110
RCC AHB1 Peripheral Clock Register (RCC_AHB1ENR)
112
RCC AHB2 Peripheral Clock Enable Register (RCC_AHB2ENR)
114
RCC AHB3 Peripheral Clock Enable Register (RCC_AHB3ENR)
115
RCC APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
115
RCC APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
118
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB1LPENR)
120
RCC AHB2 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB2LPENR)
122
RCC AHB3 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB3LPENR)
123
RCC APB1 Peripheral Clock Enable in Low Power Mode Register (RCC_APB1LPENR)
124
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register (RCC_APB2LPENR)
127
RCC Backup Domain Control Register (RCC_BDCR)
129
RCC Clock Control & Status Register (RCC_CSR)
130
RCC Spread Spectrum Clock Generation Register (RCC_SSCGR)
132
RCC PLLI2S Configuration Register (RCC_PLLI2SCFGR)
133
RCC Register Map
135
Table 13. RCC Register Map and Reset Values
135
General-Purpose I/Os (GPIO)
138
GPIO Introduction
138
GPIO Main Features
138
GPIO Functional Description
138
Figure 13. Basic Structure of a Five-Volt Tolerant I/O Port Bit
139
Table 14. Port Bit Configuration Table
139
General-Purpose I/O (GPIO)
140
I/O Pin Multiplexer and Mapping
141
Table 15. Flexible SWJ-DP Pin Assignment
142
Figure 14. Selecting an Alternate Function
143
GPIO Locking Mechanism
144
I/O Data Bitwise Handling
144
I/O Port Control Registers
144
I/O Port Data Registers
144
External Interrupt/Wakeup Lines
145
I/O Alternate Function Input/Output
145
Input Configuration
145
Figure 15. Input Floating/Pull Up/Pull down Configurations
146
Output Configuration
146
Alternate Function Configuration
147
Figure 16. Output Configuration
147
Figure 17. Alternate Function Configuration
147
Analog Configuration
148
Figure 18. High Impedance-Analog Configuration
148
Using the OSC32_IN/OSC32_OUT Pins as GPIO PC14/PC15
148
Port Pins
148
Using the OSC_IN/OSC_OUT Pins as GPIO PH0/PH1 Port Pins
148
Selection of RTC_AF1 and RTC_AF2 Alternate Functions
149
GPIO Registers
151
GPIO Port Mode Register (Gpiox_Moder) (X = A..I
151
GPIO Port Output Type Register (Gpiox_Otyper)
151
(X = a
151
GPIO Port Output Speed Register (Gpiox_Ospeedr)
152
(X = a
152
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupdr)
152
GPIO Port Input Data Register (Gpiox_Idr) (X = a
153
GPIO Port Output Data Register (Gpiox_Odr) (X = a
153
GPIO Port Bit Set/Reset Register (Gpiox_Bsrr) (X = a
153
GPIO Port Configuration Lock Register (Gpiox_Lckr)
154
(X = a
154
GPIO Alternate Function Low Register (Gpiox_Afrl) (X = a
155
(X = a
156
GPIO Register Map
157
Table 18. GPIO Register Map and Reset Values
157
System Configuration Controller (SYSCFG)
159
I/O Compensation Cell
159
SYSCFG Registers
159
SYSCFG Memory Remap Register (SYSCFG_MEMRMP)
159
SYSCFG Peripheral Mode Configuration Register (SYSCFG_PMC)
160
SYSCFG External Interrupt Configuration Register 1
160
(Syscfg_Exticr1)
160
SYSCFG External Interrupt Configuration Register 2
161
(Syscfg_Exticr2)
161
(Syscfg_Exticr3)
161
(Syscfg_Exticr4)
162
Compensation Cell Control Register (SYSCFG_CMPCR)
162
SYSCFG Register Map
163
Table 19. SYSCFG Register Map and Reset Values
163
Interrupts and Events
164
Nested Vectored Interrupt Controller (NVIC)
164
NVIC Features
164
Systick Calibration Value Register
164
Interrupt and Exception Vectors
164
Table 20. Vector Table
164
External Interrupt/Event Controller (EXTI)
168
EXTI Main Features
168
EXTI Block Diagram
169
Wakeup Event Management
169
Functional Description
169
Figure 19. External Interrupt/Event Controller Block Diagram
169
External Interrupt/Event Line Mapping
171
Figure 20. External Interrupt/Event GPIO Mapping
171
EXTI Registers
172
Interrupt Mask Register (EXTI_IMR)
172
Event Mask Register (EXTI_EMR)
172
Rising Trigger Selection Register (EXTI_RTSR)
173
Falling Trigger Selection Register (EXTI_FTSR)
173
Software Interrupt Event Register (EXTI_SWIER)
174
Pending Register (EXTI_PR)
174
EXTI Register Map
175
Table 21. External Interrupt/Event Controller Register Map and Reset Values
175
DMA Controller (DMA)
176
DMA Introduction
176
DMA Main Features
176
DMA Functional Description
178
General Description
178
Figure 21. DMA Block Diagram
178
DMA Transactions
179
Figure 22. System Implementation of the Two DMA Controllers
179
Channel Selection
180
Table 22. DMA1 Request Mapping
180
Figure 23. Channel Selection
180
Arbiter
181
DMA Streams
181
Table 23. DMA2 Request Mapping
181
Source, Destination and Transfer Modes
182
Table 24. Source and Destination Address
182
Figure 24. Peripheral-To-Memory Mode
183
Figure 25. Memory-To-Peripheral Mode
184
Pointer Incrementation
185
Figure 26. Memory-To-Memory Mode
185
Circular Mode
186
Double Buffer Mode
186
Programmable Data Width, Packing/Unpacking, Endianess
187
Table 25. Source and Destination Address Registers in Double Buffer Mode (DBM=1)
187
Table 26. Packing/Unpacking & Endian Behavior (Bit PINC = MINC = 1)
188
Single and Burst Transfers
189
Table 27. Restriction on NDT Versus PSIZE and MSIZE
189
Fifo
190
Figure 27. FIFO Structure
190
Table 28. FIFO Threshold Configurations
191
DMA Transfer Completion
192
DMA Transfer Suspension
193
Flow Controller
194
Summary of the Possible DMA Configurations
195
Stream Configuration Procedure
195
Table 29. Possible DMA Configurations
195
Error Management
196
DMA Interrupts
197
Table 30. DMA Interrupt Requests
197
DMA Registers
198
DMA Low Interrupt Status Register (DMA_LISR)
198
DMA High Interrupt Status Register (DMA_HISR)
199
DMA Low Interrupt Flag Clear Register (DMA_LIFCR)
200
DMA High Interrupt Flag Clear Register (DMA_HIFCR)
200
DMA Stream X Configuration Register (Dma_Sxcr) (X = 0
201
DMA Stream X Number of Data Register (Dma_Sxndtr) (X = 0
204
DMA Stream X Peripheral Address Register (Dma_Sxpar) (X = 0
205
DMA Stream X Memory 0 Address Register (Dma_Sxm0Ar) (X = 0
205
DMA Stream X Memory 1 Address Register (Dma_Sxm1Ar) (X = 0
205
DMA Stream X FIFO Control Register (Dma_Sxfcr) (X = 0
206
DMA Register Map
208
Table 31. DMA Register Map and Reset Values
208
Analog-To-Digital Converter (ADC)
212
ADC Introduction
212
ADC Main Features
212
ADC Functional Description
213
Figure 28. Single ADC Block Diagram
213
ADC Clock
214
ADC On-Off Control
214
Channel Selection
214
Table 32. ADC Pins
214
Continuous Conversion Mode
215
Single Conversion Mode
215
Analog Watchdog
216
Figure 29. Timing Diagram
216
Figure 30. Analog Watchdog's Guarded Area
216
Timing Diagram
216
Injected Channel Management
217
Scan Mode
217
Table 33. Analog Watchdog Channel Selection
217
Discontinuous Mode
218
Figure 31. Injected Conversion Latency
218
Data Alignment
220
Figure 32. Right Alignment of 12-Bit Data
220
Figure 33. Left Alignment of 12-Bit Data
220
Figure 34. Left Alignment of 6-Bit Data
220
Channel-Wise Programmable Sampling Time
221
Conversion on External Trigger and Trigger Polarity
221
Table 34. Configuring the Trigger Polarity
221
Table 35. External Trigger for Regular Channels
222
Fast Conversion Mode
223
Table 36. External Trigger for Injected Channels
223
Data Management
224
Using the DMA
224
Managing a Sequence of Conversions Without Using the DMA
224
Conversions Without DMA and Without Overrun Detection
225
Multi ADC Mode
225
Figure 35. Multi ADC Block Diagram
226
Injected Simultaneous Mode
228
Figure 36. Injected Simultaneous Mode on 4 Channels: Dual ADC Mode
229
Figure 37. Injected Simultaneous Mode on 4 Channels: Triple ADC Mode
229
Regular Simultaneous Mode
229
Figure 38. Regular Simultaneous Mode on 16 Channels: Dual ADC Mode
230
Figure 39. Regular Simultaneous Mode on 16 Channels: Triple ADC Mode
230
Figure 40. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Dual ADC Mode
231
Interleaved Mode
231
Alternate Trigger Mode
232
Figure 41. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Triple ADC Mode
232
Figure 42. Alternate Trigger: Injected Group of each ADC
233
Combined Regular/Injected Simultaneous Mode
234
Figure 43. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Mode
234
Figure 44. Alternate Trigger: Injected Group of each ADC
234
Combined Regular Simultaneous + Alternate Trigger Mode
235
Figure 45. Alternate + Regular Simultaneous
235
Temperature Sensor
236
Figure 46. Case of Trigger Occurring During Injected Conversion
236
Figure 47. Temperature Sensor and VREFINT Channel Block Diagram
237
Battery Charge Monitoring
238
ADC Interrupts
238
Table 37. ADC Interrupts
238
ADC Registers
239
ADC Status Register (ADC_SR)
239
ADC Control Register 1 (ADC_CR1)
240
ADC Control Register 2 (ADC_CR2)
242
ADC Sample Time Register 1 (ADC_SMPR1)
244
ADC Sample Time Register 2 (ADC_SMPR2)
244
ADC Injected Channel Data Offset Register X (Adc_Jofrx) (X=1
245
ADC Watchdog Higher Threshold Register (ADC_HTR)
245
ADC Watchdog Lower Threshold Register (ADC_LTR)
246
ADC Regular Sequence Register 1 (ADC_SQR1)
246
ADC Regular Sequence Register 2 (ADC_SQR2)
247
ADC Regular Sequence Register 3 (ADC_SQR3)
247
ADC Injected Sequence Register (ADC_JSQR)
248
ADC Injected Data Register X (Adc_Jdrx) (X= 1
249
ADC Regular Data Register (ADC_DR)
249
ADC Common Status Register (ADC_CSR)
250
ADC Common Control Register (ADC_CCR)
250
10.13.17 ADC Common Regular Data Register for Dual and Triple Modes
253
(Adc_Cdr)
253
10.13.18 ADC Register Map
253
Table 38. ADC Global Register Map
253
Table 39. ADC Register Map and Reset Values for each ADC
254
Table 40. ADC Register Map and Reset Values (Common ADC Registers)
255
Digital-To-Analog Converter (DAC)
256
DAC Introduction
256
DAC Main Features
256
Table 41. DAC Pins
257
Figure 48. DAC Channel Block Diagram
257
DAC Functional Description
258
DAC Channel Enable
258
DAC Output Buffer Enable
258
DAC Data Format
258
DAC Conversion
259
Figure 49. Data Registers in Single DAC Channel Mode
259
Figure 50. Data Registers in Dual DAC Channel Mode
259
DAC Output Voltage
260
DAC Trigger Selection
260
Table 42. External Triggers
260
Figure 51. Timing Diagram for Conversion with Trigger Disabled TEN = 0
260
DMA Request
261
Noise Generation
261
Triangle-Wave Generation
262
Figure 52. DAC LFSR Register Calculation Algorithm
262
Figure 53. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
262
Dual DAC Channel Conversion
263
Figure 54. DAC Triangle Wave Generation
263
Figure 55. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
263
Independent Trigger with Different LFSR Generation
264
Independent Trigger with Single LFSR Generation
264
Independent Trigger Without Wave Generation
264
Independent Trigger with Different Triangle Generation
265
Independent Trigger with Single Triangle Generation
265
Simultaneous Software Start
265
Simultaneous Trigger with Different LFSR Generation
266
Simultaneous Trigger with Single LFSR Generation
266
Simultaneous Trigger Without Wave Generation
266
Simultaneous Trigger with Different Triangle Generation
267
Simultaneous Trigger with Single Triangle Generation
267
DAC Registers
268
DAC Control Register (DAC_CR)
268
DAC Software Trigger Register (DAC_SWTRIGR)
271
DAC Channel1 12-Bit Right-Aligned Data Holding Register (DAC_DHR12R1)
271
DAC Channel1 12-Bit Left Aligned Data Holding Register
272
(Dac_Dhr12L1)
272
DAC Channel2 12-Bit Left Aligned Data Holding Register
273
(Dac_Dhr12L2)
273
Dual DAC 12-Bit Right-Aligned Data Holding Register (DAC_DHR12RD)
274
DUAL DAC 12-Bit Left Aligned Data Holding Register
274
(Dac_Dhr12Ld)
274
DAC Channel1 Data Output Register (DAC_DOR1)
275
DAC Channel2 Data Output Register (DAC_DOR2)
275
DAC Status Register (DAC_SR)
276
DAC Register Map
276
Table 43. DAC Register Map
276
Digital Camera Interface (DCMI)
278
DCMI Introduction
278
DCMI Main Features
278
DCMI Pins
278
DCMI Clocks
278
Table 44. DCMI Pins
278
DCMI Functional Overview
279
Figure 56. DCMI Block Diagram
279
DCMI Physical Interface
280
DMA Interface
280
Figure 57. Top-Level Block Diagram
280
Table 45. DCMI Signals
280
Figure 58. DCMI Signal Waveforms
281
Table 46. Positioning of Captured Data Bytes in 32-Bit Words (8-Bit Width)
281
Table 47. Positioning of Captured Data Bytes in 32-Bit Words (10-Bit Width)
281
Synchronization
282
Table 48. Positioning of Captured Data Bytes in 32-Bit Words (12-Bit Width)
282
Table 49. Positioning of Captured Data Bytes in 32-Bit Words (14-Bit Width)
282
Figure 59. Timing Diagram
283
Capture Modes
285
Figure 60. Frame Capture Waveforms in Snapshot Mode
285
Crop Feature
286
Figure 61. Frame Capture Waveforms in Continuous Grab Mode
286
Figure 62. Coordinates and Size of the Window after Cropping
287
Figure 63. Data Capture Waveforms
287
Fifo
288
JPEG Format
288
Data Format Description
288
Data Formats
288
Figure 64. Pixel Raster Scan Order
288
Monochrome Format
289
RGB Format
289
Ycbcr Format
289
Table 50. Data Storage in Monochrome Progressive Video Format
289
Table 51. Data Storage in RGB Progressive Video Format
289
DCMI Interrupts
290
DCMI Register Description
290
DCMI Control Register 1 (DCMI_CR)
290
Table 52. Data Storage in Ycbcr Progressive Video Format
290
Table 53. DCMI Interrupts
290
DCMI Status Register (DCMI_SR)
293
DCMI Raw Interrupt Status Register (DCMI_RIS)
294
DCMI Interrupt Enable Register (DCMI_IER)
295
DCMI Masked Interrupt Status Register (DCMI_MIS)
296
DCMI Interrupt Clear Register (DCMI_ICR)
297
DCMI Embedded Synchronization Code Register (DCMI_ESCR)
298
DCMI Embedded Synchronization Unmask Register (DCMI_ESUR)
299
DCMI Crop Window Start (DCMI_CWSTRT)
300
DCMI Crop Window Size (DCMI_CWSIZE)
300
DCMI Data Register (DCMI_DR)
301
DCMI Register Map
301
Table 54. DCMI Register Map and Reset Values
301
Advertisement
ST STM32F207 series Reference Manual (1381 pages)
Advanced Arm-based 32-bit MCUs
Brand:
ST
| Category:
Microcontrollers
| Size: 18 MB
Table of Contents
Table of Contents
2
SYSCFG External Interrupt Configuration Register
4
List of Tables
32
Documentation Conventions
46
General Information
46
Glossary
46
List of Abbreviations for Registers
46
Peripheral Availability
47
Memory and Bus Architecture
48
System Architecture
48
Figure 1. System Architecture
49
S0: I-Bus
49
S1: D-Bus
49
S2: S-Bus
49
S3, S4: DMA Memory Bus
49
AHB/APB Bridges (APB)
50
Busmatrix
50
Memory Organization
50
S5: DMA Peripheral Bus
50
S6: Ethernet DMA Bus
50
S7: USB OTG HS DMA Bus
50
Memory Map
51
Table 1. Stm32F20X and Stm32F21X Register Boundary Addresses
51
Embedded SRAM
53
Bit Banding
54
Embedded Flash Memory
55
Flash Memory Read Interface
55
Table 2. Flash Module Organization
55
Table 3. Number of Wait States According to Cortex ® -M3 Clock Frequency
56
Adaptive Real-Time Memory Accelerator (ART Accelerator™)
58
Boot Configuration
58
Table 4. Boot Modes
58
Table 5. Memory Mapping Vs. Boot Mode/Physical Remap
59
CRC Calculation Unit
61
CRC Introduction
61
CRC Main Features
61
Figure 2. CRC Calculation Unit Block Diagram
61
CRC Functional Description
62
CRC Registers
62
Data Register (CRC_DR)
62
Independent Data Register (CRC_IDR)
62
Control Register (CRC_CR)
63
CRC Register Map
63
Table 6. CRC Calculation Unit Register Map and Reset Values
63
Figure 3. Power Supply Overview
64
Power Control (PWR)
64
Power Supplies
64
Battery Backup Domain
65
Independent A/D Converter Supply and Reference Voltage
65
Table 17. RTC_AF2 Pin
66
Figure 4. Backup SRAM
67
Voltage Regulator
67
Figure 5. Power-On/Power-Down Reset Waveform
68
Power Supply Supervisor
68
Power-On Reset (Por)/Power-Down Reset (PDR)
68
Brownout Reset (BOR)
69
Figure 6. BOR Thresholds
69
Programmable Voltage Detector (PVD)
69
Figure 7. PVD Thresholds
70
Low-Power Modes
70
Peripheral Clock Gating
72
Slowing down System Clocks
72
Table 7. Low-Power Mode Summary
72
Sleep Mode
73
Table 8. Sleep-Now
73
Table 9. Sleep-On-Exit
73
Stop Mode
74
Table 10. Stop Mode
75
Standby Mode
76
Table 11. Standby Mode
77
Table 16. RTC_AF1 Pin
77
Programming the RTC Alternate Functions to Wake up the Device from the Stop and Standby Modes
78
Power Control Registers
80
PWR Power Control Register (PWR_CR)
80
PWR Power Control/Status Register (PWR_CSR)
81
PWR Register Map
83
Table 12. PWR - Register Map and Reset Values
83
Reset
84
Reset and Clock Control (RCC)
84
System Reset
84
Figure 8. Simplified Diagram of the Reset Circuit
85
Power Reset
85
Backup Domain Reset
86
Clocks
86
Figure 9. Clock Tree
87
HSE Clock
88
Figure 10. HSE/ LSE Clock Sources
89
HSI Clock
89
LSE Clock
90
PLL Configuration
90
Clock Security System (CSS)
91
LSI Clock
91
System Clock (SYSCLK) Selection
91
RTC/AWU Clock
92
Watchdog Clock
92
Clock-Out Capability
93
Internal/External Clock Measurement Using TIM5/TIM11
93
Figure 11. Frequency Measurement with TIM5 in Input Capture Mode
94
Figure 12. Frequency Measurement with TIM11 in Input Capture Mode
94
RCC Clock Control Register (RCC_CR)
95
RCC Registers
95
RCC PLL Configuration Register (RCC_PLLCFGR)
97
RCC Clock Configuration Register (RCC_CFGR)
99
RCC Clock Interrupt Register (RCC_CIR)
101
RCC AHB1 Peripheral Reset Register (RCC_AHB1RSTR)
104
RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR)
106
RCC AHB3 Peripheral Reset Register (RCC_AHB3RSTR)
107
RCC APB1 Peripheral Reset Register (RCC_APB1RSTR)
107
RCC APB2 Peripheral Reset Register (RCC_APB2RSTR)
110
RCC AHB1 Peripheral Clock Register (RCC_AHB1ENR)
112
RCC AHB2 Peripheral Clock Enable Register (RCC_AHB2ENR)
114
RCC AHB3 Peripheral Clock Enable Register (RCC_AHB3ENR)
115
RCC APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
115
RCC APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
118
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB1LPENR)
120
RCC AHB2 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB2LPENR)
122
RCC AHB3 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB3LPENR)
123
RCC APB1 Peripheral Clock Enable in Low Power Mode Register (RCC_APB1LPENR)
124
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register (RCC_APB2LPENR)
127
RCC Backup Domain Control Register (RCC_BDCR)
129
RCC Clock Control & Status Register (RCC_CSR)
130
RCC Spread Spectrum Clock Generation Register (RCC_SSCGR)
132
RCC PLLI2S Configuration Register (RCC_PLLI2SCFGR)
133
RCC Register Map
135
Table 13. RCC Register Map and Reset Values
135
General-Purpose I/Os (GPIO)
138
GPIO Functional Description
138
GPIO Introduction
138
GPIO Main Features
138
Figure 13. Basic Structure of a Five-Volt Tolerant I/O Port Bit
139
Table 14. Port Bit Configuration Table
139
General-Purpose I/O (GPIO)
140
I/O Pin Multiplexer and Mapping
141
Table 15. Flexible SWJ-DP Pin Assignment
142
Figure 14. Selecting an Alternate Function
143
GPIO Locking Mechanism
144
I/O Data Bitwise Handling
144
I/O Port Control Registers
144
I/O Port Data Registers
144
External Interrupt/Wakeup Lines
145
I/O Alternate Function Input/Output
145
Input Configuration
145
Figure 15. Input Floating/Pull Up/Pull down Configurations
146
Output Configuration
146
Alternate Function Configuration
147
Figure 16. Output Configuration
147
Figure 17. Alternate Function Configuration
147
Analog Configuration
148
Figure 18. High Impedance-Analog Configuration
148
Port Pins
148
Using the OSC32_IN/OSC32_OUT Pins as GPIO PC14/PC15
148
Using the OSC_IN/OSC_OUT Pins as GPIO PH0/PH1 Port Pins
148
Selection of RTC_AF1 and RTC_AF2 Alternate Functions
149
(X = a
151
GPIO Port Mode Register (Gpiox_Moder) (X = A..I
151
GPIO Port Output Type Register (Gpiox_Otyper)
151
GPIO Registers
151
(X = a
152
GPIO Port Output Speed Register (Gpiox_Ospeedr)
152
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupdr)
152
GPIO Port Bit Set/Reset Register (Gpiox_Bsrr) (X = a
153
GPIO Port Input Data Register (Gpiox_Idr) (X = a
153
GPIO Port Output Data Register (Gpiox_Odr) (X = a
153
(X = a
154
GPIO Port Configuration Lock Register (Gpiox_Lckr)
154
GPIO Alternate Function Low Register (Gpiox_Afrl) (X = a
155
(X = a
156
GPIO Register Map
157
Table 18. GPIO Register Map and Reset Values
157
I/O Compensation Cell
159
SYSCFG Memory Remap Register (SYSCFG_MEMRMP)
159
SYSCFG Registers
159
System Configuration Controller (SYSCFG)
159
(Syscfg_Exticr1)
160
SYSCFG External Interrupt Configuration Register 1
160
SYSCFG Peripheral Mode Configuration Register (SYSCFG_PMC)
160
(Syscfg_Exticr2)
161
(Syscfg_Exticr3)
161
SYSCFG External Interrupt Configuration Register 2
161
(Syscfg_Exticr4)
162
Compensation Cell Control Register (SYSCFG_CMPCR)
162
SYSCFG Register Map
163
Table 19. SYSCFG Register Map and Reset Values
163
Interrupt and Exception Vectors
164
Interrupts and Events
164
Nested Vectored Interrupt Controller (NVIC)
164
NVIC Features
164
Systick Calibration Value Register
164
Table 20. Vector Table
164
External Interrupt/Event Controller (EXTI)
168
EXTI Main Features
168
EXTI Block Diagram
169
Figure 19. External Interrupt/Event Controller Block Diagram
169
Functional Description
169
Wakeup Event Management
169
External Interrupt/Event Line Mapping
171
Figure 20. External Interrupt/Event GPIO Mapping
171
Event Mask Register (EXTI_EMR)
172
EXTI Registers
172
Interrupt Mask Register (EXTI_IMR)
172
Falling Trigger Selection Register (EXTI_FTSR)
173
Rising Trigger Selection Register (EXTI_RTSR)
173
Pending Register (EXTI_PR)
174
Software Interrupt Event Register (EXTI_SWIER)
174
EXTI Register Map
175
Table 21. External Interrupt/Event Controller Register Map and Reset Values
175
DMA Controller (DMA)
176
DMA Introduction
176
DMA Main Features
176
DMA Functional Description
178
Figure 21. DMA Block Diagram
178
General Description
178
DMA Transactions
179
Figure 22. System Implementation of the Two DMA Controllers
179
Channel Selection
180
Figure 23. Channel Selection
180
Table 22. DMA1 Request Mapping
180
Arbiter
181
DMA Streams
181
Table 23. DMA2 Request Mapping
181
Source, Destination and Transfer Modes
182
Table 24. Source and Destination Address
182
Figure 24. Peripheral-To-Memory Mode
183
Figure 25. Memory-To-Peripheral Mode
184
Figure 26. Memory-To-Memory Mode
185
Pointer Incrementation
185
Circular Mode
186
Double Buffer Mode
186
Programmable Data Width, Packing/Unpacking, Endianess
187
Table 25. Source and Destination Address Registers in Double Buffer Mode (DBM=1)
187
Table 26. Packing/Unpacking & Endian Behavior (Bit PINC = MINC = 1)
188
Single and Burst Transfers
189
Table 27. Restriction on NDT Versus PSIZE and MSIZE
189
Fifo
190
Figure 27. FIFO Structure
190
Table 28. FIFO Threshold Configurations
191
DMA Transfer Completion
192
DMA Transfer Suspension
193
Flow Controller
194
Stream Configuration Procedure
195
Summary of the Possible DMA Configurations
195
Table 29. Possible DMA Configurations
195
Error Management
196
DMA Interrupts
197
Table 30. DMA Interrupt Requests
197
DMA Low Interrupt Status Register (DMA_LISR)
198
DMA Registers
198
DMA High Interrupt Status Register (DMA_HISR)
199
DMA High Interrupt Flag Clear Register (DMA_HIFCR)
200
DMA Low Interrupt Flag Clear Register (DMA_LIFCR)
200
DMA Stream X Configuration Register (Dma_Sxcr) (X = 0
201
DMA Stream X Number of Data Register (Dma_Sxndtr) (X = 0
204
DMA Stream X Memory 0 Address Register (Dma_Sxm0Ar) (X = 0
205
DMA Stream X Memory 1 Address Register (Dma_Sxm1Ar) (X = 0
205
DMA Stream X Peripheral Address Register (Dma_Sxpar) (X = 0
205
DMA Stream X FIFO Control Register (Dma_Sxfcr) (X = 0
206
DMA Register Map
208
Table 31. DMA Register Map and Reset Values
208
ADC Introduction
212
ADC Main Features
212
Analog-To-Digital Converter (ADC)
212
ADC Functional Description
213
Figure 28. Single ADC Block Diagram
213
ADC Clock
214
ADC On-Off Control
214
Channel Selection
214
Table 32. ADC Pins
214
Continuous Conversion Mode
215
Single Conversion Mode
215
Analog Watchdog
216
Figure 29. Timing Diagram
216
Figure 30. Analog Watchdog's Guarded Area
216
Timing Diagram
216
Injected Channel Management
217
Scan Mode
217
Table 33. Analog Watchdog Channel Selection
217
Discontinuous Mode
218
Figure 31. Injected Conversion Latency
218
Data Alignment
220
Figure 32. Right Alignment of 12-Bit Data
220
Figure 33. Left Alignment of 12-Bit Data
220
Figure 34. Left Alignment of 6-Bit Data
220
Channel-Wise Programmable Sampling Time
221
Conversion on External Trigger and Trigger Polarity
221
Table 34. Configuring the Trigger Polarity
221
Table 35. External Trigger for Regular Channels
222
Fast Conversion Mode
223
Table 36. External Trigger for Injected Channels
223
Data Management
224
Managing a Sequence of Conversions Without Using the DMA
224
Using the DMA
224
Conversions Without DMA and Without Overrun Detection
225
Multi ADC Mode
225
Figure 35. Multi ADC Block Diagram
226
Injected Simultaneous Mode
228
Figure 36. Injected Simultaneous Mode on 4 Channels: Dual ADC Mode
229
Figure 37. Injected Simultaneous Mode on 4 Channels: Triple ADC Mode
229
Regular Simultaneous Mode
229
Figure 38. Regular Simultaneous Mode on 16 Channels: Dual ADC Mode
230
Figure 39. Regular Simultaneous Mode on 16 Channels: Triple ADC Mode
230
Figure 40. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Dual ADC Mode
231
Interleaved Mode
231
Alternate Trigger Mode
232
Figure 41. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Triple ADC Mode
232
Figure 42. Alternate Trigger: Injected Group of each ADC
233
Combined Regular/Injected Simultaneous Mode
234
Figure 43. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Mode
234
Figure 44. Alternate Trigger: Injected Group of each ADC
234
Combined Regular Simultaneous + Alternate Trigger Mode
235
Figure 45. Alternate + Regular Simultaneous
235
Figure 46. Case of Trigger Occurring During Injected Conversion
236
Temperature Sensor
236
Figure 47. Temperature Sensor and VREFINT Channel Block Diagram
237
ADC Interrupts
238
Battery Charge Monitoring
238
Table 37. ADC Interrupts
238
ADC Registers
239
ADC Status Register (ADC_SR)
239
ADC Control Register 1 (ADC_CR1)
240
ADC Control Register 2 (ADC_CR2)
242
ADC Sample Time Register 1 (ADC_SMPR1)
244
ADC Sample Time Register 2 (ADC_SMPR2)
244
ADC Injected Channel Data Offset Register X (Adc_Jofrx) (X=1
245
ADC Watchdog Higher Threshold Register (ADC_HTR)
245
ADC Regular Sequence Register 1 (ADC_SQR1)
246
ADC Watchdog Lower Threshold Register (ADC_LTR)
246
ADC Regular Sequence Register 2 (ADC_SQR2)
247
ADC Regular Sequence Register 3 (ADC_SQR3)
247
ADC Injected Sequence Register (ADC_JSQR)
248
ADC Injected Data Register X (Adc_Jdrx) (X= 1
249
ADC Regular Data Register (ADC_DR)
249
ADC Common Control Register (ADC_CCR)
250
ADC Common Status Register (ADC_CSR)
250
(Adc_Cdr)
253
10.13.17 ADC Common Regular Data Register for Dual and Triple Modes
253
10.13.18 ADC Register Map
253
Table 38. ADC Global Register Map
253
Table 39. ADC Register Map and Reset Values for each ADC
254
Table 40. ADC Register Map and Reset Values (Common ADC Registers)
255
DAC Introduction
256
DAC Main Features
256
Digital-To-Analog Converter (DAC)
256
Figure 48. DAC Channel Block Diagram
257
Table 41. DAC Pins
257
DAC Channel Enable
258
DAC Data Format
258
DAC Functional Description
258
DAC Output Buffer Enable
258
DAC Conversion
259
Figure 49. Data Registers in Single DAC Channel Mode
259
Figure 50. Data Registers in Dual DAC Channel Mode
259
DAC Output Voltage
260
DAC Trigger Selection
260
Figure 51. Timing Diagram for Conversion with Trigger Disabled TEN = 0
260
Table 42. External Triggers
260
DMA Request
261
Noise Generation
261
Figure 52. DAC LFSR Register Calculation Algorithm
262
Figure 53. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
262
Triangle-Wave Generation
262
Dual DAC Channel Conversion
263
Figure 54. DAC Triangle Wave Generation
263
Figure 55. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
263
Independent Trigger with Different LFSR Generation
264
Independent Trigger with Single LFSR Generation
264
Independent Trigger Without Wave Generation
264
Independent Trigger with Different Triangle Generation
265
Independent Trigger with Single Triangle Generation
265
Simultaneous Software Start
265
Simultaneous Trigger with Different LFSR Generation
266
Simultaneous Trigger with Single LFSR Generation
266
Simultaneous Trigger Without Wave Generation
266
Simultaneous Trigger with Different Triangle Generation
267
Simultaneous Trigger with Single Triangle Generation
267
DAC Control Register (DAC_CR)
268
DAC Registers
268
DAC Channel1 12-Bit Right-Aligned Data Holding Register (DAC_DHR12R1)
271
DAC Software Trigger Register (DAC_SWTRIGR)
271
(Dac_Dhr12L1)
272
DAC Channel1 12-Bit Left Aligned Data Holding Register
272
DAC Channel1 8-Bit Right Aligned Data Holding Register
272
(Dac_Dhr12L2)
273
DAC Channel2 12-Bit Left Aligned Data Holding Register
273
DAC Channel2 12-Bit Right Aligned Data Holding Register
273
DAC Channel2 8-Bit Right-Aligned Data Holding Register
273
(Dac_Dhr12Ld)
274
DUAL DAC 12-Bit Left Aligned Data Holding Register
274
Dual DAC 12-Bit Right-Aligned Data Holding Register (DAC_DHR12RD)
274
DAC Channel1 Data Output Register (DAC_DOR1)
275
DAC Channel2 Data Output Register (DAC_DOR2)
275
DUAL DAC 8-Bit Right Aligned Data Holding Register
275
DAC Register Map
276
DAC Status Register (DAC_SR)
276
Table 43. DAC Register Map
276
DCMI Clocks
278
DCMI Introduction
278
DCMI Main Features
278
DCMI Pins
278
Digital Camera Interface (DCMI)
278
Table 44. DCMI Pins
278
DCMI Functional Overview
279
Figure 56. DCMI Block Diagram
279
DCMI Physical Interface
280
DMA Interface
280
Figure 57. Top-Level Block Diagram
280
Table 45. DCMI Signals
280
Figure 58. DCMI Signal Waveforms
281
Table 46. Positioning of Captured Data Bytes in 32-Bit Words (8-Bit Width)
281
Table 47. Positioning of Captured Data Bytes in 32-Bit Words (10-Bit Width)
281
Synchronization
282
Table 48. Positioning of Captured Data Bytes in 32-Bit Words (12-Bit Width)
282
Table 49. Positioning of Captured Data Bytes in 32-Bit Words (14-Bit Width)
282
Figure 59. Timing Diagram
283
Capture Modes
285
Figure 60. Frame Capture Waveforms in Snapshot Mode
285
Crop Feature
286
Figure 61. Frame Capture Waveforms in Continuous Grab Mode
286
Figure 62. Coordinates and Size of the Window after Cropping
287
Figure 63. Data Capture Waveforms
287
Data Format Description
288
Data Formats
288
Fifo
288
Figure 64. Pixel Raster Scan Order
288
JPEG Format
288
Monochrome Format
289
RGB Format
289
Table 50. Data Storage in Monochrome Progressive Video Format
289
Table 51. Data Storage in RGB Progressive Video Format
289
Ycbcr Format
289
DCMI Control Register 1 (DCMI_CR)
290
DCMI Interrupts
290
DCMI Register Description
290
Table 52. Data Storage in Ycbcr Progressive Video Format
290
Table 53. DCMI Interrupts
290
DCMI Status Register (DCMI_SR)
293
DCMI Raw Interrupt Status Register (DCMI_RIS)
294
DCMI Interrupt Enable Register (DCMI_IER)
295
DCMI Masked Interrupt Status Register (DCMI_MIS)
296
DCMI Interrupt Clear Register (DCMI_ICR)
297
DCMI Embedded Synchronization Code Register (DCMI_ESCR)
298
DCMI Embedded Synchronization Unmask Register (DCMI_ESUR)
299
DCMI Crop Window Size (DCMI_CWSIZE)
300
DCMI Crop Window Start (DCMI_CWSTRT)
300
DCMI Data Register (DCMI_DR)
301
DCMI Register Map
301
Table 54. DCMI Register Map and Reset Values
301
Advanced-Control Timers (TIM1 and TIM8)
303
TIM1 and TIM8 Introduction
303
TIM1 and TIM8 Main Features
304
Figure 65. Advanced-Control Timer Block Diagram
305
TIM1 and TIM8 Functional Description
306
Time-Base Unit
306
Figure 66. Counter Timing Diagram with Prescaler Division Change from 1 to 2
307
Figure 67. Counter Timing Diagram with Prescaler Division Change from 1 to 4
307
Counter Modes
308
Figure 68. Counter Timing Diagram, Internal Clock Divided by 1
308
Figure 69. Counter Timing Diagram, Internal Clock Divided by 2
309
Figure 70. Counter Timing Diagram, Internal Clock Divided by 4
309
Figure 71. Counter Timing Diagram, Internal Clock Divided by N
309
Figure 72. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
310
Figure 73. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
310
Figure 74. Counter Timing Diagram, Internal Clock Divided by 1
312
Figure 75. Counter Timing Diagram, Internal Clock Divided by 2
312
Figure 76. Counter Timing Diagram, Internal Clock Divided by 4
313
Figure 77. Counter Timing Diagram, Internal Clock Divided by N
313
Figure 78. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
314
Figure 79. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
315
Figure 80. Counter Timing Diagram, Internal Clock Divided by 2
315
Figure 81. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
316
Figure 82. Counter Timing Diagram, Internal Clock Divided by N
316
Figure 83. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
317
Figure 84. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
317
Repetition Counter
317
Figure 85. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
318
Clock Selection
319
Figure 86. Control Circuit in Normal Mode, Internal Clock Divided by 1
319
Figure 87. TI2 External Clock Connection Example
320
Figure 88. Control Circuit in External Clock Mode 1
321
Figure 89. External Trigger Input Block
321
Capture/Compare Channels
322
Figure 90. Control Circuit in External Clock Mode 2
322
Figure 91. Capture/Compare Channel (Example: Channel 1 Input Stage)
323
Figure 92. Capture/Compare Channel 1 Main Circuit
323
Figure 93. Output Stage of Capture/Compare Channel (Channel 1 to 3)
324
Figure 94. Output Stage of Capture/Compare Channel (Channel 4)
324
Input Capture Mode
325
Figure 95. PWM Input Mode Timing
326
Forced Output Mode
326
PWM Input Mode
326
Output Compare Mode
327
Figure 96. Output Compare Mode, Toggle on OC1
328
PWM Mode
328
Figure 97. Edge-Aligned PWM Waveforms (ARR=8)
329
Figure 98. Center-Aligned PWM Waveforms (ARR=8)
330
Complementary Outputs and Dead-Time Insertion
331
Figure 100. Dead-Time Waveforms with Delay Greater than the Negative Pulse
332
Figure 101. Dead-Time Waveforms with Delay Greater than the Positive Pulse
332
Figure 99. Complementary Output with Dead-Time Insertion
332
Using the Break Function
333
Figure 102. Output Behavior in Response to a Break
335
Clearing the Ocxref Signal on an External Event
336
Figure 103. Clearing Timx Ocxref
336
6-Step PWM Generation
337
Figure 104. 6-Step Generation, COM Example (OSSR=1)
337
Figure 105. Example of One Pulse Mode
338
One-Pulse Mode
338
Encoder Interface Mode
339
Table 55. Counting Direction Versus Encoder Signals
340
Figure 106. Example of Counter Operation in Encoder Interface Mode
341
Figure 107. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
341
Interfacing with Hall Sensors
342
Timer Input XOR Function
342
Figure 108. Example of Hall Sensor Interface
343
Figure 109. Control Circuit in Reset Mode
344
Timx and External Trigger Synchronization
344
Figure 110. Control Circuit in Gated Mode
345
Figure 111. Control Circuit in Trigger Mode
346
Debug Mode
347
Figure 112. Control Circuit in External Clock Mode 2 + Trigger Mode
347
Timer Synchronization
347
TIM1 and TIM8 Control Register 1 (Timx_Cr1)
348
TIM1 and TIM8 Registers
348
TIM1 and TIM8 Control Register 2 (Timx_Cr2)
349
TIM1 and TIM8 Slave Mode Control Register (Timx_Smcr)
352
Table 56. Timx Internal Trigger Connection
354
TIM1 and TIM8 Dma/Interrupt Enable Register (Timx_Dier)
354
TIM1 and TIM8 Status Register (Timx_Sr)
356
TIM1 and TIM8 Event Generation Register (Timx_Egr)
357
TIM1 and TIM8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
359
TIM1 and TIM8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
362
TIM1 and TIM8 Capture/Compare Enable Register (Timx_Ccer)
363
Table 57. Output Control Bits for Complementary Ocx and Ocxn Channels with
366
TIM1 and TIM8 Auto-Reload Register (Timx_Arr)
367
TIM1 and TIM8 Counter (Timx_Cnt)
367
TIM1 and TIM8 Prescaler (Timx_Psc)
367
TIM1 and TIM8 Capture/Compare Register 1 (Timx_Ccr1)
368
TIM1 and TIM8 Repetition Counter Register (Timx_Rcr)
368
TIM1 and TIM8 Capture/Compare Register 2 (Timx_Ccr2)
369
TIM1 and TIM8 Capture/Compare Register 3 (Timx_Ccr3)
369
TIM1 and TIM8 Break and Dead-Time Register (Timx_Bdtr)
370
TIM1 and TIM8 Capture/Compare Register 4 (Timx_Ccr4)
370
TIM1 and TIM8 DMA Control Register (Timx_Dcr)
372
TIM1 and TIM8 DMA Address for Full Transfer (Timx_Dmar)
373
Table 58. TIM1 and TIM8 Register Map and Reset Values
374
TIM1 and TIM8 Register Map
374
General-Purpose Timers (TIM2 to TIM5)
376
TIM2 to TIM5 Introduction
376
TIM2 to TIM5 Main Features
376
Figure 113. General-Purpose Timer Block Diagram
377
TIM2 to TIM5 Functional Description
378
Time-Base Unit
378
Counter Modes
379
Figure 114. Counter Timing Diagram with Prescaler Division Change from 1 to 2
379
Figure 115. Counter Timing Diagram with Prescaler Division Change from 1 to 4
379
Figure 116. Counter Timing Diagram, Internal Clock Divided by 1
380
Figure 117. Counter Timing Diagram, Internal Clock Divided by 2
380
Figure 118. Counter Timing Diagram, Internal Clock Divided by 4
381
Figure 119. Counter Timing Diagram, Internal Clock Divided by N
381
Figure 120. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
382
Figure 121. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
382
Figure 122. Counter Timing Diagram, Internal Clock Divided by 1
383
Figure 123. Counter Timing Diagram, Internal Clock Divided by 2
384
Figure 124. Counter Timing Diagram, Internal Clock Divided by 4
384
Figure 125. Counter Timing Diagram, Internal Clock Divided by N
384
Figure 126. Counter Timing Diagram, Update Event
385
Figure 127. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
386
Figure 128. Counter Timing Diagram, Internal Clock Divided by 2
386
Figure 129. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
387
Figure 130. Counter Timing Diagram, Internal Clock Divided by N
387
Figure 131. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
388
Figure 132. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
388
Clock Selection
389
Figure 133. Control Circuit in Normal Mode, Internal Clock Divided by 1
389
Figure 134. TI2 External Clock Connection Example
390
Figure 135. Control Circuit in External Clock Mode 1
391
Figure 136. External Trigger Input Block
391
Capture/Compare Channels
392
Figure 137. Control Circuit in External Clock Mode 2
392
Figure 138. Capture/Compare Channel (Example: Channel 1 Input Stage)
392
Figure 139. Capture/Compare Channel 1 Main Circuit
393
Figure 140. Output Stage of Capture/Compare Channel (Channel 1)
393
Input Capture Mode
394
Figure 141. PWM Input Mode Timing
395
PWM Input Mode
395
Forced Output Mode
396
Output Compare Mode
396
Figure 142. Output Compare Mode, Toggle on OC1
397
PWM Mode
397
Figure 143. Edge-Aligned PWM Waveforms (ARR=8)
398
Figure 144. Center-Aligned PWM Waveforms (ARR=8)
399
Figure 145. Example of One-Pulse Mode
400
One-Pulse Mode
400
Clearing the Ocxref Signal on an External Event
401
Encoder Interface Mode
402
Figure 146. Clearing Timx Ocxref
402
Table 59. Counting Direction Versus Encoder Signals
403
Figure 147. Example of Counter Operation in Encoder Interface Mode
404
Figure 148. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
404
Figure 149. Control Circuit in Reset Mode
405
Timer Input XOR Function
405
Timers and External Trigger Synchronization
405
Figure 150. Control Circuit in Gated Mode
406
Figure 151. Control Circuit in Trigger Mode
407
Figure 152. Control Circuit in External Clock Mode 2 + Trigger Mode
408
Figure 153. Master/Slave Timer Example
408
Timer Synchronization
408
Figure 154. Gating Timer 2 with OC1REF of Timer 1
409
Figure 155. Gating Timer 2 with Enable of Timer 1
410
Figure 156. Triggering Timer 2 with Update of Timer 1
411
Figure 157. Triggering Timer 2 with Enable of Timer 1
412
Debug Mode
413
Figure 158. Triggering Timer 1 and 2 with Timer 1 TI1 Input
413
TIM2 to TIM5 Registers
414
Timx Control Register 1 (Timx_Cr1)
414
Timx Control Register 2 (Timx_Cr2)
416
Timx Slave Mode Control Register (Timx_Smcr)
417
Table 60. Timx Internal Trigger Connection
419
Timx Dma/Interrupt Enable Register (Timx_Dier)
419
Timx Status Register (Timx_Sr)
420
Timx Event Generation Register (Timx_Egr)
422
Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
423
Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
426
Timx Capture/Compare Enable Register (Timx_Ccer)
427
Table 61. Output Control Bit for Standard Ocx Channels
428
Timx Auto-Reload Register (Timx_Arr)
429
Timx Counter (Timx_Cnt)
429
Timx Prescaler (Timx_Psc)
429
Timx Capture/Compare Register 1 (Timx_Ccr1)
430
Timx Capture/Compare Register 2 (Timx_Ccr2)
430
Timx Capture/Compare Register 3 (Timx_Ccr3)
431
Timx Capture/Compare Register 4 (Timx_Ccr4)
431
Timx DMA Control Register (Timx_Dcr)
432
Timx DMA Address for Full Transfer (Timx_Dmar)
433
TIM2 Option Register (TIM2_OR)
434
TIM5 Option Register (TIM5_OR)
434
Table 62. TIM2 to TIM5 Register Map and Reset Values
435
Timx Register Map
435
General-Purpose Timers (TIM9 to TIM14)
437
TIM9 to TIM14 Introduction
437
TIM9 to TIM14 Main Features
437
TIM9/TIM12 Main Features
437
Figure 159. General-Purpose Timer Block Diagram (TIM9 and TIM12)
438
TIM10/TIM11 and TIM13/TIM14 Main Features
438
Figure 160. General-Purpose Timer Block Diagram (TIM10/11/13/14)
439
TIM9 to TIM14 Functional Description
440
Time-Base Unit
440
Figure 161. Counter Timing Diagram with Prescaler Division Change from 1 to 2
441
Figure 162. Counter Timing Diagram with Prescaler Division Change from 1 to 4
441
Counter Modes
442
Figure 163. Counter Timing Diagram, Internal Clock Divided by 1
442
Figure 164. Counter Timing Diagram, Internal Clock Divided by 2
443
Figure 165. Counter Timing Diagram, Internal Clock Divided by 4
443
Figure 166. Counter Timing Diagram, Internal Clock Divided by N
443
Figure 167. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
444
Figure 168. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
444
Clock Selection
445
Figure 169. Control Circuit in Normal Mode, Internal Clock Divided by 1
445
Figure 170. TI2 External Clock Connection Example
446
Figure 171. Control Circuit in External Clock Mode 1
446
Capture/Compare Channels
447
Figure 172. Capture/Compare Channel (Example: Channel 1 Input Stage)
447
Figure 173. Capture/Compare Channel 1 Main Circuit
448
Figure 174. Output Stage of Capture/Compare Channel (Channel 1)
448
Input Capture Mode
448
Figure 175. PWM Input Mode Timing
450
PWM Input Mode (Only for TIM9/12)
450
Forced Output Mode
451
Output Compare Mode
451
Figure 176. Output Compare Mode, Toggle on OC1
452
PWM Mode
452
Figure 177. Edge-Aligned PWM Waveforms (ARR=8)
453
One-Pulse Mode
453
Figure 178. Example of One Pulse Mode
454
TIM9/12 External Trigger Synchronization
455
Figure 179. Control Circuit in Reset Mode
456
Figure 180. Control Circuit in Gated Mode
457
Figure 181. Control Circuit in Trigger Mode
457
Debug Mode
458
Timer Synchronization (TIM9/12)
458
TIM9 and TIM12 Registers
459
TIM9/12 Control Register 1 (Timx_Cr1)
459
TIM9/12 Control Register 2 (Timx_Cr2)
460
TIM9/12 Slave Mode Control Register (Timx_Smcr)
461
Table 63. Timx Internal Trigger Connection
462
TIM9/12 Interrupt Enable Register (Timx_Dier)
462
TIM9/12 Status Register (Timx_Sr)
464
TIM9/12 Event Generation Register (Timx_Egr)
465
TIM9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)
466
TIM9/12 Capture/Compare Enable Register (Timx_Ccer)
469
Table 64. Output Control Bit for Standard Ocx Channels
470
TIM9/12 Auto-Reload Register (Timx_Arr)
470
TIM9/12 Counter (Timx_Cnt)
470
TIM9/12 Prescaler (Timx_Psc)
470
TIM9/12 Capture/Compare Register 1 (Timx_Ccr1)
471
TIM9/12 Capture/Compare Register 2 (Timx_Ccr2)
471
Table 65. TIM9/12 Register Map and Reset Values
472
TIM9/12 Register Map
472
TIM10/11/13/14 Control Register 1 (Timx_Cr1)
474
TIM10/11/13/14 Registers
474
TIM10/11/13/14 Interrupt Enable Register (Timx_Dier)
475
TIM10/11/13/14 Status Register (Timx_Sr)
475
TIM10/11/13/14 Capture/Compare Mode Register 1 (Timx_Ccmr1)
476
TIM10/11/13/14 Event Generation Register (Timx_Egr)
476
Table 66. Output Control Bit for Standard Ocx Channels
479
TIM10/11/13/14 Capture/Compare Enable Register (Timx_Ccer)
479
TIM10/11/13/14 Auto-Reload Register (Timx_Arr)
480
TIM10/11/13/14 Counter (Timx_Cnt)
480
TIM10/11/13/14 Prescaler (Timx_Psc)
480
TIM10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)
481
TIM11 Option Register 1 (TIM11_OR)
481
Table 67. TIM10/11/13/14 Register Map and Reset Values
482
TIM10/11/13/14 Register Map
482
Basic Timers (TIM6 and TIM7)
484
Figure 182. Basic Timer Block Diagram
484
TIM6 and TIM7 Introduction
484
TIM6 and TIM7 Main Features
484
TIM6 and TIM7 Functional Description
485
Time-Base Unit
485
Figure 183. Counter Timing Diagram with Prescaler Division Change from 1 to 2
486
Figure 184. Counter Timing Diagram with Prescaler Division Change from 1 to 4
486
Counting Mode
487
Figure 185. Counter Timing Diagram, Internal Clock Divided by 1
487
Figure 186. Counter Timing Diagram, Internal Clock Divided by 2
488
Figure 187. Counter Timing Diagram, Internal Clock Divided by 4
488
Figure 188. Counter Timing Diagram, Internal Clock Divided by N
488
Clock Source
489
Debug Mode
490
Figure 191. Control Circuit in Normal Mode, Internal Clock Divided by 1
490
TIM6 and TIM7 Control Register 1 (Timx_Cr1)
490
TIM6 and TIM7 Registers
490
TIM6 and TIM7 Control Register 2 (Timx_Cr2)
492
TIM6 and TIM7 Dma/Interrupt Enable Register (Timx_Dier)
492
TIM6 and TIM7 Counter (Timx_Cnt)
493
TIM6 and TIM7 Event Generation Register (Timx_Egr)
493
TIM6 and TIM7 Status Register (Timx_Sr)
493
TIM6 and TIM7 Auto-Reload Register (Timx_Arr)
494
TIM6 and TIM7 Prescaler (Timx_Psc)
494
Table 68. TIM6 and TIM7 Register Map and Reset Values
495
TIM6 and TIM7 Register Map
495
Hardware Watchdog
496
Independent Watchdog (IWDG)
496
IWDG Functional Description
496
IWDG Introduction
496
IWDG Main Features
496
Debug Mode
497
Figure 192. Independent Watchdog Block Diagram
497
Register Access Protection
497
Table 69. Min/Max IWDG Timeout Period (in Ms) at 32 Khz (LSI)
497
IWDG Registers
498
Key Register (IWDG_KR)
498
Prescaler Register (IWDG_PR)
498
Reload Register (IWDG_RLR)
499
Status Register (IWDG_SR)
499
IWDG Register Map
500
Table 70. IWDG Register Map and Reset Values
500
Window Watchdog (WWDG)
501
WWDG Functional Description
501
WWDG Introduction
501
WWDG Main Features
501
Figure 193. Watchdog Block Diagram
502
Figure 194. Window Watchdog Timing Diagram
503
How to Program the Watchdog Timeout
503
Debug Mode
504
Table 71. Table
504
Control Register (WWDG_CR)
505
WWDG Registers
505
Configuration Register (WWDG_CFR)
506
Status Register (WWDG_SR)
506
WWDG Register Map
507
CRYP Introduction
508
CRYP Main Features
508
Cryptographic Processor (CRYP)
508
Table 73. Number of Cycles Required to Process each 128-Bit Block
508
CRYP Functional Description
510
DES/TDES Cryptographic Core
510
Figure 195. Block Diagram
510
Figure 196. DES/TDES-ECB Mode Encryption
512
Figure 197. DES/TDES-ECB Mode Decryption
512
Figure 198. DES/TDES-CBC Mode Encryption
514
AES Cryptographic Core
515
Figure 199. DES/TDES-CBC Mode Decryption
515
Figure 200. AES-ECB Mode Encryption
516
Figure 201. AES-ECB Mode Decryption
517
Figure 202. AES-CBC Mode Encryption
518
Figure 203. AES-CBC Mode Decryption
519
Figure 204. AES-CTR Mode Encryption
520
Figure 205. AES-CTR Mode Decryption
521
Figure 206. Initial Counter Block Structure for the Counter Mode
521
Data Type
522
Table 74. Data Types
522
Figure 207. 64-Bit Block Construction According to DATATYPE
524
Initialization Vectors - CRYP_IV0
524
CRYP Busy State
526
Figure 208. Initialization Vectors Use in the TDES-CBC Encryption
526
Procedure to Perform an Encryption or a Decryption
527
Context Swapping
528
CRYP Interrupts
530
CRYP Control Register (CRYP_CR)
531
CRYP DMA Interface
531
CRYP Registers
531
Figure 209. CRYP Interrupt Mapping Diagram
531
CRYP Status Register (CRYP_SR)
534
CRYP Data Input Register (CRYP_DIN)
535
CRYP Data Output Register (CRYP_DOUT)
536
CRYP DMA Control Register (CRYP_DMACR)
537
CRYP Interrupt Mask Set/Clear Register (CRYP_IMSCR)
537
CRYP Masked Interrupt Status Register (CRYP_MISR)
538
CRYP Raw Interrupt Status Register (CRYP_RISR)
538
CRYP Key Registers (CRYP_K0
539
CRYP Initialization Vector Registers (CRYP_IV0
541
CRYP Register Map
542
Table 75. CRYP Register Map and Reset Values
542
Figure 210. Block Diagram
544
Random Number Generator (RNG)
544
RNG Functional Description
544
RNG Introduction
544
RNG Main Features
544
Error Management
545
Operation
545
RNG Registers
545
RNG Control Register (RNG_CR)
546
RNG Status Register (RNG_SR)
546
RNG Data Register (RNG_DR)
547
RNG Register Map
548
Table 76. RNG Register Map and Reset Map
548
HASH Functional Description
549
HASH Introduction
549
HASH Main Features
549
Hash Processor (HASH)
549
Figure 211. Block Diagram
550
Figure 212. Block Diagram
551
Data Type
552
Duration of the Processing
552
Figure 213. Bit, Byte and Half-Word Swapping
553
Message Digest Computing
554
Message Padding
555
Hash Operation
556
HMAC Operation
556
Context Swapping
557
Figure 214. HASH Interrupt Mapping Diagram
558
HASH Interrupt
558
HASH Control Register (HASH_CR)
559
HASH Registers
559
HASH Data Input Register (HASH_DIN)
562
HASH Start Register (HASH_STR)
563
HASH Digest Registers (HASH_HR0
564
HASH Interrupt Enable Register (HASH_IMR)
565
HASH Status Register (HASH_SR)
566
HASH Context Swap Registers (Hash_Csrx)
567
HASH Register Map
568
Table 77. HASH Register Map and Reset Values
568
Introduction
570
Real-Time Clock (RTC)
570
Figure 215. RTC Block Diagram
571
RTC Main Features
571
Clock and Prescalers
572
RTC Functional Description
572
Periodic Auto-Wakeup
573
Programmable Alarms
573
Real-Time Clock and Calendar
573
RTC Initialization and Configuration
574
Reading the Calendar
576
Resetting the RTC
576
RTC Reference Clock Detection
577
RTC Coarse Digital Calibration
578
Timestamp Function
578
Tamper Detection
579
Calibration Clock Output
580
Alarm Output
581
RTC and Low-Power Modes
581
RTC Interrupts
581
Table 78. Effect of Low-Power Modes on RTC
581
Table 79. Interrupt Control Bits
582
RTC Registers
583
RTC Time Register (RTC_TR)
583
RTC Date Register (RTC_DR)
584
RTC Control Register (RTC_CR)
585
RTC Initialization and Status Register (RTC_ISR)
587
RTC Prescaler Register (RTC_PRER)
589
RTC Wakeup Timer Register (RTC_WUTR)
589
RTC Calibration Register (RTC_CALIBR)
590
RTC Alarm a Register (RTC_ALRMAR)
591
RTC Alarm B Register (RTC_ALRMBR)
592
RTC Time Stamp Time Register (RTC_TSTR)
593
RTC Write Protection Register (RTC_WPR)
593
RTC Time Stamp Date Register (RTC_TSDR)
594
(Rtc_Tafcr)
595
RTC Tamper and Alternate Function Configuration Register
595
RTC Backup Registers (Rtc_Bkpxr)
596
RTC Register Map
596
Table 80. RTC Register Map and Reset Values
596
I 2 C Introduction
598
I 2 C Main Features
598
Inter-Integrated Circuit (I2C) Interface
598
I 2 C Functional Description
599
Mode Selection
599
Figure 216. I2C Bus Protocol
600
Figure 217. I2C Block Diagram
601
I2C Slave Mode
601
Figure 218. Transfer Sequence Diagram for Slave Transmitter
603
Figure 219. Transfer Sequence Diagram for Slave Receiver
604
I2C Master Mode
604
Figure 220. Transfer Sequence Diagram for Master Transmitter
607
Figure 221. Transfer Sequence Diagram for Master Receiver
608
Error Conditions
609
SDA/SCL Line Control
610
Smbus
610
Table 81. Smbus Vs. I2C
611
DMA Requests
613
I 2 C Interrupts
615
Packet Error Checking
615
Table 82. I2C Interrupt Requests
615
Figure 222. I2C Interrupt Mapping Diagram
616
I 2 C Control Register 1 (I2C_CR1)
617
I 2 C Debug Mode
617
I 2 C Registers
617
I 2 C Control Register 2 (I2C_CR2)
619
I 2 C Own Address Register 1 (I2C_OAR1)
621
I 2 C Own Address Register 2 (I2C_OAR2)
621
C Data Register (I2C_DR)
622
C Status Register 1 (I2C_SR1)
622
C Status Register 2 (I2C_SR2)
625
C Clock Control Register (I2C_CCR)
627
I 2 C TRISE Register (I2C_TRISE)
628
I2C Register Map
629
Table 83. I2C Register Map and Reset Values
629
Transmitter (USART)
630
Universal Synchronous Asynchronous Receiver
630
USART Introduction
630
USART Main Features
630
USART Functional Description
631
Figure 223. USART Block Diagram
633
Figure 224. Word Length Programming
634
USART Character Description
634
Transmitter
635
Figure 225. Configurable Stop Bits
636
Figure 226. TC/TXE Behavior When Transmitting
637
Figure 227. Start Bit Detection When Oversampling by 16 or 8
638
Receiver
638
Figure 228. Data Sampling When Oversampling by 16
641
Figure 229. Data Sampling When Oversampling by 8
642
Table 84. Noise Detection from Sampled Data
642
Fractional Baud Rate Generation
643
USART Receiver Tolerance to Clock Deviation
651
Multiprocessor Communication
652
Table 93. USART Receiver's Tolerance When DIV Fraction Is 0
652
Table 94. USART Receiver Tolerance When Div_Fraction Is Different from 0
652
Figure 230. Mute Mode Using Idle Line Detection
653
Figure 231. Mute Mode Using Address Mark Detection
653
Parity Control
654
Table 95. Frame Formats
654
LIN (Local Interconnection Network) Mode
655
Figure 232. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)
656
Figure 233. Break Detection in LIN Mode Vs. Framing Error Detection
657
USART Synchronous Mode
657
Figure 234. USART Example of Synchronous Transmission
658
Figure 235. USART Data Clock Timing Diagram (M=0)
658
Figure 236. USART Data Clock Timing Diagram (M=1)
659
Figure 237. RX Data Setup/Hold Time
659
Single-Wire Half-Duplex Communication
659
Figure 238. ISO 7816-3 Asynchronous Protocol
660
Smartcard
660
Figure 239. Parity Error Detection Using the 1.5 Stop Bits
661
Irda SIR ENDEC Block
662
Figure 240. Irda SIR ENDEC- Block Diagram
663
Figure 241. Irda Data Modulation (3/16) -Normal Mode
663
Continuous Communication Using DMA
664
Figure 242. Transmission Using DMA
665
Figure 243. Reception Using DMA
666
Figure 244. Hardware Flow Control between 2 Usarts
666
Hardware Flow Control
666
Figure 245. RTS Flow Control
667
Figure 246. CTS Flow Control
668
Figure 247. USART Interrupt Mapping Diagram
669
Table 96. USART Interrupt Requests
669
USART Interrupts
669
Status Register (USART_SR)
670
Table 97. USART Mode Configuration
670
USART Mode Configuration
670
USART Registers
670
Baud Rate Register (USART_BRR)
673
Control Register 1 (USART_CR1)
673
Data Register (USART_DR)
673
Control Register 2 (USART_CR2)
676
Control Register 3 (USART_CR3)
677
Guard Time and Prescaler Register (USART_GTPR)
680
Table 98. USART Register Map and Reset Values
681
USART Register Map
681
Serial Peripheral Interface (SPI)
682
SPI Introduction
682
SPI and I 2 S Main Features
683
SPI Features
683
I 2 S Features
684
Figure 248. SPI Block Diagram
685
General Description
685
SPI Functional Description
685
Figure 249. Single Master/ Single Slave Application
686
Figure 250. Data Clock Timing Diagram
688
Configuring the SPI in Slave Mode
689
Figure 251. TI Mode - Slave Mode, Single Transfer
690
Configuring the SPI in Master Mode
691
Figure 252. TI Mode - Slave Mode, Continuous Transfer
691
Figure 253. TI Mode - Master Mode, Single Transfer
692
Configuring the SPI for Half-Duplex Communication
693
Figure 254. TI Mode - Master Mode, Continuous Transfer
693
Data Transmission and Reception Procedures
694
Figure 255. TXE/RXNE/BSY Behavior in Master / Full-Duplex Mode
696
Figure 256. TXE/RXNE/BSY Behavior in Slave / Full-Duplex Mode
697
Figure 257. TXE/BSY Behavior in Master Transmit-Only Mode (BIDIMODE=0 and RXONLY=0)
698
Figure 258. TXE/BSY in Slave Transmit-Only Mode (BIDIMODE=0 and RXONLY=0) in Case of
698
Figure 259. RXNE Behavior in Receive-Only Mode (BIDIRMODE=0 and RXONLY=1)
699
CRC Calculation
700
Figure 260. TXE/BSY Behavior When Transmitting (BIDIRMODE=0 and RXONLY=0)
700
Status Flags
702
Disabling the SPI
703
SPI Communication Using DMA (Direct Memory Addressing)
704
Figure 261. Transmission Using DMA
705
Figure 262. Reception Using DMA
705
Error Flags
706
Figure 263. TI Mode Frame Format Error Detection
707
SPI Interrupts
707
Table 99. SPI Interrupt Requests
707
Figure 264. I 2 S Block Diagram
708
S Functional Description
708
S General Description
708
Supported Audio Protocols
709
Figure 265. I S Philips Protocol Waveforms (16/32-Bit Full Accuracy, CPOL = 0)
710
Figure 266. I S Philips Standard Waveforms (24-Bit Frame with CPOL = 0)
710
Figure 267. Transmitting 0X8Eaa33
711
Figure 268. Receiving 0X8Eaa33
711
Figure 269. I
711
Figure 270. Example
711
Figure 271. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length with CPOL = 0
712
Figure 272. MSB Justified 24-Bit Frame Length with CPOL = 0
712
Figure 273. MSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
713
Figure 274. LSB Justified 16-Bit or 32-Bit Full-Accuracy with CPOL = 0
713
Figure 275. LSB Justified 24-Bit Frame Length with CPOL = 0
713
Figure 276. Operations Required to Transmit 0X3478Ae
714
Figure 277. Operations Required to Receive 0X3478Ae
714
Figure 278. LSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
714
Figure 279. Example of LSB Justified 16-Bit Extended to 32-Bit Packet Frame
715
Figure 280. PCM Standard Waveforms (16-Bit)
715
Clock Generator
716
Figure 281. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)
716
Figure 282. Audio Sampling Frequency Definition
716
Figure 283. I
717
Table 100. Audio Frequency Precision (for PLLM VCO = 1 Mhz or 2 Mhz)
717
I 2 S Master Mode
718
I 2 S Slave Mode
720
Status Flags
722
Error Flags
723
I 2 S Interrupts
723
Table 101. I
723
DMA Features
724
SPI and I S Registers
725
SPI Control Register 1 (SPI_CR1) (Not Used in I 2 S Mode)
725
SPI Control Register 2 (SPI_CR2)
727
SPI Status Register (SPI_SR)
728
SPI Data Register (SPI_DR)
729
Mode)
730
SPI CRC Polynomial Register (SPI_CRCPR) (Not Used in I
730
SPI RX CRC Register (SPI_RXCRCR) (Not Used in I 2 S Mode)
730
SPI TX CRC Register (SPI_TXCRCR) (Not Used in I 2 S Mode)
731
SPI_I S Configuration Register (SPI_I2SCFGR)
731
SPI_I S Prescaler Register (SPI_I2SPR)
733
SPI Register Map
734
Table 102. SPI Register Map and Reset Values
734
SDIO Main Features
735
Secure Digital Input/Output Interface (SDIO)
735
Figure 284. SDIO "No Response" and "No Data" Operations
736
Figure 285. SDIO (Multiple) Block Read Operation
736
SDIO Bus Topology
736
Figure 286. SDIO (Multiple) Block Write Operation
737
Figure 287. SDIO Sequential Read Operation
737
Figure 288. SDIO Sequential Write Operation
737
Figure 289. SDIO Block Diagram
738
SDIO Functional Description
738
Figure 290. SDIO Adapter
739
SDIO Adapter
739
Table 103. SDIO I/O Definitions
739
Figure 291. Control Unit
740
Figure 292. SDIO Adapter Command Path
741
Figure 293. Command Path State Machine (CPSM)
742
Figure 294. SDIO Command Transfer
743
Table 104. Command Format
743
Table 105. Short Response Format
744
Table 106. Long Response Format
744
Table 107. Command Path Status Flags
744
Figure 295. Data Path
745
Figure 296. Data Path State Machine (DPSM)
746
Table 108. Data Token Format
747
Table 109. Transmit FIFO Status Flags
748
SDIO APB2 Interface
749
Table 110. Receive FIFO Status Flags
749
Card Functional Description
750
Card Identification Mode
750
Card Reset
750
Operating Voltage Range Validation
750
Card Identification Process
751
Block Write
752
Block Read
753
Stream Access, Stream Write and Stream Read (Multimediacard Only)
753
Erase: Group Erase and Sector Erase
755
Protection Management
755
Wide Bus Selection or Deselection
755
Card Status Register
758
Table 111. Card Status
759
SD Status Register
761
Table 112. SD Status
762
Table 113. Speed Class Code Field
763
Table 114. Performance Move Field
763
Table 115. AU_SIZE Field
764
Table 116. Maximum AU Size
764
Table 117. Erase Size Field
764
SD I/O Mode
765
Table 118. Erase Timeout Field
765
Table 119. Erase Offset Field
765
Commands and Responses
766
Table 120. Block-Oriented Write Commands
767
Table 121. Block-Oriented Write Protection Commands
768
Table 122. Erase Commands
768
Table 123. I/O Mode Commands
769
Table 124. Lock Card
769
Table 125. Application-Specific Commands
769
R1 (Normal Response Command)
770
R1B
770
R2 (CID, CSD Register)
770
Response Formats
770
Table 126. R1 Response
770
R3 (OCR Register)
771
R4 (Fast I/O)
771
Table 127. R2 Response
771
Table 128. R3 Response
771
Table 129. R4 Response
771
R4B
772
R5 (Interrupt Request)
772
Table 130. R4B Response
772
Table 131. R5 Response
772
SDIO I/O Card-Specific Operations
773
Table 132. R6 Response
773
SDIO I/O Read Wait Operation by SDIO_D2 Signaling
774
SDIO Interrupts
774
SDIO Read Wait Operation by Stopping SDIO_CK
774
SDIO Suspend/Resume Operation
774
Aborting CMD61
775
CE-ATA Interrupt
775
CE-ATA Specific Operations
775
Command Completion Signal Disable
775
Command Completion Signal Enable
775
HW Flow Control
776
SDIO Power Control Register (SDIO_POWER)
776
SDIO Registers
776
SDI Clock Control Register (SDIO_CLKCR)
777
SDIO Argument Register (SDIO_ARG)
778
SDIO Command Register (SDIO_CMD)
778
SDIO Command Response Register (SDIO_RESPCMD)
779
SDIO Data Timer Register (SDIO_DTIMER)
780
SDIO Response 1
780
Table 133. Response Type and Sdio_Respx Registers
780
SDIO Data Length Register (SDIO_DLEN)
781
SDIO Data Control Register (SDIO_DCTRL)
782
SDIO Data Counter Register (SDIO_DCOUNT)
783
SDIO Status Register (SDIO_STA)
784
SDIO Interrupt Clear Register (SDIO_ICR)
785
SDIO Mask Register (SDIO_MASK)
787
SDIO FIFO Counter Register (SDIO_FIFOCNT)
789
SDIO Data FIFO Register (SDIO_FIFO)
790
SDIO Register Map
790
Table 134. SDIO Register Map
790
Bxcan Introduction
792
Bxcan Main Features
792
Controller Area Network (Bxcan)
792
Bxcan General Description
793
CAN 2.0B Active Core
793
Figure 297. CAN Network Topology
793
Acceptance Filters
794
Control, Status and Configuration Registers
794
Tx Mailboxes
794
Bxcan Operating Modes
795
Figure 298. Dual CAN Block Diagram
795
Initialization Mode
796
Normal Mode
796
Sleep Mode (Low-Power)
796
Figure 299. Bxcan Operating Modes
797
Silent Mode
797
Test Mode
797
Figure 300. Bxcan in Silent Mode
798
Figure 301. Bxcan in Loop Back Mode
798
Loop Back Combined with Silent Mode
798
Loop Back Mode
798
Bxcan Functional Description
799
Debug Mode
799
Figure 302. Bxcan in Combined Mode
799
Transmission Handling
799
Figure 303. Transmit Mailbox States
801
Reception Handling
801
Time Triggered Communication Mode
801
Figure 304. Receive FIFO States
802
Identifier Filtering
803
Figure 305. Filter Bank Scale Configuration - Register Organization
804
Figure 306. Example of Filter Numbering
805
Figure 307. Filtering Mechanism - Example
806
Message Storage
807
Table 135. Transmit Mailbox Mapping
807
Table 136. Receive Mailbox Mapping
807
Figure 308. CAN Error State Diagram
808
Bit Timing
809
Error Management
809
Figure 309. Bit Timing
810
Bxcan Interrupts
811
Figure 310. CAN Frames
811
Figure 311. Event Flags and Interrupt Generation
812
CAN Control and Status Registers
813
CAN Registers
813
Register Access Protection
813
CAN Mailbox Registers
823
Figure 312. RX and TX Mailboxes
823
CAN Filter Registers
830
Bxcan Register Map
834
Table 137. Bxcan Register Map and Reset Values
834
DMA Controller
838
Ethernet (ETH): Media Access Control (MAC) with
838
Ethernet Introduction
838
Ethernet Main Features
838
MAC Core Features
839
DMA Features
840
PTP Features
840
Ethernet Pins
841
Table 138. Alternate Function Mapping
841
Ethernet Functional Description: SMI, MII and RMII
842
Figure 313. ETH Block Diagram
842
Station Management Interface: SMI
842
Figure 314. SMI Interface Signals
843
Table 139. Management Frame Format
843
Figure 315. MDIO Timing and Frame Structure - Write Cycle
844
Figure 316. MDIO Timing and Frame Structure - Read Cycle
845
Figure 317. Media Independent Interface Signals
845
Media-Independent Interface: MII
845
Table 140. Clock Range
845
Table 141. TX Interface Signal Encoding
846
Figure 318. MII Clock Sources
847
Reduced Media-Independent Interface: RMII
847
Table 142. RX Interface Signal Encoding
847
Figure 319. Reduced Media-Independent Interface Signals
848
Figure 320. RMII Clock Sources
848
Ethernet Functional Description: MAC 802.3
849
Figure 321. Clock Scheme
849
MII/RMII Selection
849
MAC 802.3 Frame Format
850
Figure 322. Address Field Format
851
Figure 323. MAC Frame Format
853
Figure 324. Tagged MAC Frame Format
853
MAC Frame Transmission
854
Figure 325. Transmission Bit Order
860
Figure 326. Transmission with no Collision
860
Figure 327. Transmission with Collision
861
Figure 328. Frame Transmission in MMI and RMII Modes
861
MAC Frame Reception
861
Table 143. Frame Statuses
863
Figure 329. Receive Bit Order
865
Figure 330. Reception with no Error
866
Figure 331. Reception with Errors
866
Figure 332. Reception with False Carrier Indication
866
MAC Interrupts
866
Figure 333. MAC Core Interrupt Masking Scheme
867
MAC Filtering
867
Table 144. Destination Address Filtering
869
MAC Loopback Mode
870
MAC Management Counters: MMC
870
Table 145. Source Address Filtering
870
Figure 334. Wakeup Frame Filter Register
871
Power Management: PMT
871
Precision Time Protocol (IEEE1588 PTP)
874
Figure 335. Networked Time Synchronization
875
Figure 336. System Time Update Using the Fine Correction Method
877
Figure 337. PTP Trigger Output to TIM2 ITR1 Connection
879
Ethernet Functional Description: DMA Controller Operation
880
Figure 338. PPS Output
880
Figure 339. Descriptor Ring and Chain Structure
881
Host Bus Burst Access
881
Initialization of a Transfer Using DMA
881
Buffer Size Calculations
882
Host Data Buffer Alignment
882
DMA Arbiter
883
Error Response to DMA
883
Tx DMA Configuration
883
Figure 340. Txdma Operation in Default Mode
885
Figure 341. Txdma Operation in OSF Mode
887
Figure 342. Normal Transmit Descriptor
888
Figure 343. Enhanced Transmit Descriptor
894
Rx DMA Configuration
895
Figure 344. Receive DMA Operation
896
Figure 345. Normal Rx DMA Descriptor Structure
898
Table 146. Receive Descriptor 0 - Encoding for Bits 7, 5 and
901
Figure 346. Enhanced Receive Descriptor Field Format with IEEE1588 Time Stamp Enabled
904
DMA Interrupts
906
Ethernet Interrupts
907
Figure 347. Interrupt Scheme
907
Ethernet Register Descriptions
908
MAC Register Description
908
Figure 348. Ethernet MAC Remote Wakeup Frame Filter Register (ETH_MACRWUFFR)
917
MMC Register Description
927
IEEE 1588 Time Stamp Registers
932
Table 147. Time Stamp Snapshot Dependency on Registers Bits
934
DMA Register Description
940
Ethernet Register Maps
953
Table 148. Ethernet Register Map and Reset Values
953
OTG_FS Introduction
957
USB On-The-Go Full-Speed (OTG_FS)
957
General Features
958
OTG_FS Main Features
958
Host-Mode Features
959
Peripheral-Mode Features
959
Figure 349. OTG Full-Speed Block Diagram
960
OTG Full-Speed Core
960
OTG Pins
960
OTG_FS Functional Description
960
Table 149. OTG_FS Input/Output Pins
960
Full-Speed OTG PHY
961
Figure 350. OTG A-B Device Connection
962
HNP Dual Role Device
962
ID Line Detection
962
OTG Dual Role Device (DRD)
962
SRP Dual Role Device
963
USB Peripheral
963
Figure 351. USB Peripheral-Only Connection
964
Peripheral States
964
SRP-Capable Peripheral
964
Peripheral Endpoints
965
USB Host
967
Figure 352. USB Host-Only Connection
968
SRP-Capable Host
968
USB Host States
968
Host Channels
970
Host Scheduler
971
Figure 353. SOF Connectivity
972
Host Sofs
972
SOF Trigger
972
OTG Low-Power Modes
973
Peripheral Sofs
973
Table 150. Compatibility of STM32 Low Power Modes with the OTG
973
Dynamic Update of the OTG_FS_HFIR Register
974
Figure 354. Updating OTG_FS_HFIR Dynamically
975
USB Data Fifos
975
Figure 355. Device-Mode FIFO Address Mapping and AHB FIFO Access Mapping
976
Peripheral FIFO Architecture
976
Peripheral Rx FIFO
976
Figure 356. Host-Mode FIFO Address Mapping and AHB FIFO Access Mapping
977
Host FIFO Architecture
977
Host Rx FIFO
977
Peripheral Tx Fifos
977
Device Mode
978
FIFO RAM Allocation
978
Host Tx Fifos
978
Host Mode
979
USB System Performance
979
OTG_FS Interrupts
980
Figure 357. Interrupt Hierarchy
981
OTG_FS Control and Status Registers
982
CSR Memory Map
983
Figure 358. CSR Memory Map
983
Table 151. Core Global Control and Status Registers (Csrs)
983
Table 152. Host-Mode Control and Status Registers (Csrs)
984
Table 153. Device-Mode Control and Status Registers
985
Table 154. Data FIFO (DFIFO) Access Register Map
986
Table 155. Power and Clock Gating Control and Status Registers
987
OTG_FS Global Registers
988
Table 156. TRDT Values
993
Host-Mode Registers
1009
Device-Mode Registers
1019
Table 157. Minimum Duration for Soft Disconnect
1021
(Otg_Fs_Pcgcctl)
1042
OTG_FS Power and Clock Gating Control Register
1042
OTG_FS Register Map
1043
Table 158. OTG_FS Register Map and Reset Values
1043
Core Initialization
1052
OTG_FS Programming Model
1052
Device Initialization
1053
Host Initialization
1053
Host Programming Model
1054
Figure 359. Transmit FIFO Write Task
1055
Figure 360. Receive FIFO Read Task
1056
Figure 361. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions
1057
Figure 362. Bulk/Control in Transactions
1060
Figure 363. Normal Interrupt OUT/IN Transactions
1062
Figure 364. Normal Isochronous OUT/IN Transactions
1067
Device Programming Model
1070
Operational Model
1072
Figure 365. Receive FIFO Packet Read
1073
Figure 366. Processing a SETUP Packet
1075
Figure 367. Bulk out Transaction
1082
Worst Case Response Time
1090
Figure 368. TRDT Max Timing Case
1091
OTG Programming Model
1091
Figure 369. A-Device SRP
1092
Figure 370. B-Device SRP
1093
Figure 371. A-Device HNP
1094
Figure 372. B-Device HNP
1096
OTG_HS Introduction
1098
OTG_HS Main Features
1098
USB On-The-Go High-Speed (OTG_HS)
1098
General Features
1099
Host-Mode Features
1100
OTG_HS Functional Description
1100
Peripheral-Mode Features
1100
Figure 373. USB OTG Interface Block Diagram
1101
High-Speed OTG PHY
1101
OTG Pins
1101
Table 159. OTG_HS Input/Output Pins
1101
Embedded Full-Speed OTG PHY
1102
HNP Dual Role Device
1102
ID Line Detection
1102
OTG Dual-Role Device
1102
SRP Dual-Role Device
1103
SRP-Capable Peripheral
1103
USB Functional Description in Peripheral Mode
1103
Peripheral States
1104
Peripheral Endpoints
1105
Figure 374. USB Host-Only Connection
1108
SRP-Capable Host
1108
USB Functional Description on Host Mode
1108
USB Host States
1109
Host Channels
1110
Host Scheduler
1112
Figure 375. SOF Trigger Output to TIM2 ITR1 Connection
1113
Host Sofs
1113
Peripheral Sofs
1113
SOF Trigger
1113
OTG_HS Low-Power Modes
1114
Table 160. Compatibility of STM32 Low Power Modes with the OTG
1114
Dynamic Update of the OTG_HS_HFIR Register
1115
Figure 376. Updating OTG_HS_HFIR Dynamically
1115
FIFO RAM Allocation
1116
Host Mode
1116
Peripheral Mode
1116
OTG_HS Interrupts
1117
Figure 377. Interrupt Hierarchy
1118
CSR Memory Map
1119
OTG_HS Control and Status Registers
1119
Figure 378. CSR Memory Map
1120
Table 161. Core Global Control and Status Registers (Csrs)
1120
Table 162. Host-Mode Control and Status Registers (Csrs)
1121
Table 163. Device-Mode Control and Status Registers
1122
OTG_HS Global Registers
1124
Table 164. Data FIFO (DFIFO) Access Register Map
1124
Table 165. Power and Clock Gating Control and Status Registers
1124
Table 166. TRDT Values
1131
Host-Mode Registers
1147
Device-Mode Registers
1160
Table 167. Minimum Duration for Soft Disconnect
1163
(Otg_Hs_Pcgcctl)
1189
OTG_HS Register Map
1189
Table 168. OTG_HS Register Map and Reset Values
1189
Core Initialization
1204
OTG_HS Programming Model
1204
Host Initialization
1205
Device Initialization
1206
DMA Mode
1206
Host Programming Model
1206
Figure 379. Transmit FIFO Write Task
1209
Figure 380. Receive FIFO Read Task
1210
Figure 381. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions - DMA
1211
Figure 382. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions - Slave
1212
Figure 383. Bulk/Control in Transactions - DMA Mode
1215
Figure 384. Bulk/Control in Transactions - Slave Mode
1216
Figure 385. Normal Interrupt OUT/IN Transactions - DMA Mode
1218
Figure 386. Normal Interrupt OUT/IN Transactions - Slave Mode
1219
Figure 387. Normal Isochronous OUT/IN Transactions - DMA Mode
1224
Figure 388. Normal Isochronous OUT/IN Transactions - Slave Mode
1225
Device Programming Model
1232
Operational Model
1234
Figure 389. Receive FIFO Packet Read in Slave Mode
1236
Figure 390. Processing a SETUP Packet
1238
Figure 391. Slave Mode Bulk out Transaction
1245
Worst Case Response Time
1253
Figure 392. TRDT Max Timing Case
1254
Figure 393. A-Device SRP
1255
OTG Programming Model
1255
Figure 394. B-Device SRP
1256
Figure 395. A-Device HNP
1257
Figure 396. B-Device HNP
1259
Flexible Static Memory Controller (FSMC)
1261
FSMC Main Features
1261
AHB Interface
1262
Block Diagram
1262
Figure 397. FSMC Block Diagram
1262
Supported Memories and Transactions
1263
External Device Address Mapping
1264
Figure 398. FSMC Memory Banks
1264
NOR/PSRAM Address Mapping
1264
NAND/PC Card Address Mapping
1265
Table 169. NOR/PSRAM Bank Selection
1265
Table 170. External Memory Address
1265
Table 171. Memory Mapping and Timing Registers
1265
NOR Flash/Psram Controller
1266
Table 172. NAND Bank Selections
1266
External Memory Interface Signals
1267
Table 173. Programmable NOR/PSRAM Access Parameters
1267
Table 174. Nonmultiplexed I/O nor Flash
1267
Table 175. Multiplexed I/O nor Flash
1268
Table 176. Nonmultiplexed I/Os PSRAM/SRAM
1268
Supported Memories and Transactions
1269
Table 177. Multiplexed I/O PSRAM
1269
Table 178. nor Flash/Psram Controller: Example of Supported Memories and Transactions
1269
General Timing Rules
1270
Figure 399. Mode1 Read Accesses
1271
Figure 400. Mode1 Write Accesses
1272
Table 179. Fsmc_Bcrx Bit Fields
1272
Figure 401. Modea Read Accesses
1273
Table 180. Fsmc_Btrx Bit Fields
1273
Figure 402. Modea Write Accesses
1274
Table 181. Fsmc_Bcrx Bit Fields
1274
Table 182. Fsmc_Btrx Bit Fields
1275
Table 183. Fsmc_Bwtrx Bit Fields
1275
Figure 403. Mode2 and Mode B Read Accesses
1276
Figure 404. Mode2 Write Accesses
1276
Figure 405. Mode B Write Accesses
1277
Table 184. Fsmc_Bcrx Bit Fields
1277
Table 185. Fsmc_Btrx Bit Fields
1278
Table 186. Fsmc_Bwtrx Bit Fields
1278
Figure 406. Mode C Read Accesses
1279
Figure 407. Mode C Write Accesses
1279
Table 187. Fsmc_Bcrx Bit Fields
1280
Table 188. Fsmc_Btrx Bit Fields
1280
Figure 408. Mode D Read Accesses
1281
Table 189. Fsmc_Bwtrx Bit Fields
1281
Figure 409. Mode D Write Accesses
1282
Table 190. Fsmc_Bcrx Bit Fields
1282
Table 191. Fsmc_Btrx Bit Fields
1283
Table 192. Fsmc_Bwtrx Bit Fields
1283
Figure 410. Multiplexed Read Accesses
1284
Figure 411. Multiplexed Write Accesses
1284
Table 193. Fsmc_Bcrx Bit Fields
1285
Table 194. Fsmc_Btrx Bit Fields
1285
Figure 412. Asynchronous Wait During a Read Access
1287
Figure 413. Asynchronous Wait During a Write Access
1287
Figure 414. Wait Configurations
1289
Figure 415. Synchronous Multiplexed Read Mode - NOR, PSRAM (CRAM)
1290
Table 195. Fsmc_Bcrx Bit Fields
1290
Table 196. Fsmc_Btrx Bit Fields
1291
Figure 416. Synchronous Multiplexed Write Mode - PSRAM (CRAM)
1292
Table 197. Fsmc_Bcrx Bit Fields
1292
Table 198. Fsmc_Btrx Bit Fields
1293
Table 199. Programmable NAND/PC Card Access Parameters
1302
Table 200. 8-Bit NAND Flash
1302
Table 201. 16-Bit NAND Flash
1303
Table 202. 16-Bit PC Card
1303
Table 203. Supported Memories and Transactions
1304
Figure 417. NAND/PC Card Controller Timing for Common Memory Access
1305
Figure 418. Access to Non 'CE Don't Care' NAND-Flash
1306
Table 204. 16-Bit PC-Card Signals and Access Type
1309
Table 205. ECC Result Relevant Bits
1316
Table 206. FSMC Register Map
1317
Figure 419. Block Diagram of STM32 MCU and Cortex
1319
Figure 420. SWJ Debug Port
1321
Table 207. SWJ Debug Port Pins
1322
Table 208. Flexible SWJ-DP Pin Assignment
1322
Figure 421. JTAG TAP Connections
1325
Table 209. JTAG Debug Port Data Registers
1327
Table 210. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
1328
Table 211. Packet Request (8-Bits)
1329
Table 212. ACK Response (3 Bits)
1330
Table 213. DATA Transfer (33 Bits)
1330
Table 214. SW-DP Registers
1331
Table 215. Cortex ® -M3 AHB-AP Registers
1332
Table 216. Core Debug Registers
1333
Table 217. Main ITM Registers
1336
Table 218. Main ETM Registers
1338
Figure 422. TPIU Block Diagram
1343
Table 219. Asynchronous TRACE Pin Assignment
1344
Table 220. Synchronous TRACE Pin Assignment
1344
Table 221. Flexible TRACE Pin Assignment
1345
Table 222. Important TPIU Registers
1347
Table 223. DBG Register Map and Reset Values
1349
Table 224. Document Revision History
1352
ST STM32F207 series Programming Manual (29 pages)
Brand:
ST
| Category:
Microcontrollers
| Size: 0 MB
Table of Contents
Table 1. Applicable Products
1
Table of Contents
2
Glossary
5
Flash Memory Interface
6
Introduction
6
Main Features
6
Flash Memory
7
Table 2. Flash Module Organization
7
Read Interface
8
Relation between CPU Clock Frequency and Flash Memory Read Time
8
Table 3. Number of Wait States According to CPU Clock (HCLK) Frequency
8
Adaptive Real-Time Memory Accelerator (ART Accelerator™)
9
Figure 2. Sequential 32-Bit Instruction Execution
10
Erase and Program Operations
11
Unlocking the Flash Control Register
11
Program/Erase Parallelism
12
Erase
12
Table 4. Program/Erase Parallelism
12
Programming
13
Interrupts
14
Option Bytes
14
Description of User Option Bytes
14
Table 5. Flash Interrupt Requests
14
Table 6. Option Byte Organization
14
Programming User Option Bytes
15
Table 7. Description of the Option Bytes
15
Read Protection (RDP)
16
Table 8. Access Versus Read Protection Level
17
Write Protections
18
One-Time Programmable Bytes
19
Table 9. OTP Part Organization
19
Flash Interface Registers
20
Flash Access Control Register (FLASH_ACR)
20
Flash Key Register (FLASH_KEYR)
21
Flash Option Key Register (FLASH_OPTKEYR)
21
Flash Status Register (FLASH_SR)
22
Flash Control Register (FLASH_CR)
23
Flash Option Control Register (FLASH_OPTCR)
24
Flash Interface Register Map
26
Table 10. Flash Register Map and Reset Values
26
Revision History
27
Table 11. Document Revision History
27
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