Clock Interrupt Enable Register (Rcc_Cier) - ST STM32L4x6 Reference Manual

RM0351
6.4.7

Clock interrupt enable register (RCC_CIER)

Address offset: 0x18
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 LSECSSIE: LSE clock security system interrupt enable
Bit 8 Reserved, must be kept at reset value.
Bit 7 PLLSAI2RDYIE: PLLSAI2 ready interrupt enable
Bit 6 PLLSAI1RDYIE: PLLSAI1 ready interrupt enable
Bit 5 PLLRDYIE: PLL ready interrupt enable
Bit 4 HSERDYIE: HSE ready interrupt enable
Bit 3 HSIRDYIE: HSI16 ready interrupt enable
28 27 26 25
Res. Res. Res.
12 11 10 9
LSE
Res. Res.
CSSIE
rw
Set and cleared by software to enable/disable interrupt caused by the clock security system
on LSE.
0: Clock security interrupt caused by LSE clock failure disabled
1: Clock security interrupt caused by LSE clock failure enabled
Set and cleared by software to enable/disable interrupt caused by PLLSAI2 lock.
0: PLLSAI2 lock interrupt disabled
1: PLLSAI2 lock interrupt enabled
Set and cleared by software to enable/disable interrupt caused by PLSAI1L lock.
0: PLLSAI1 lock interrupt disabled
1: PLLSAI1 lock interrupt enabled
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator
stabilization.
0: HSI16 ready interrupt disabled
1: HSI16 ready interrupt enabled
DocID024597 Rev 3
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
PLL PLL
PLL
Res. SAI2 SAI1
RDYIE
RDYIE RDYIE
rw rw rw
Reset and clock control (RCC)
20 19 18
Res. Res. Res. Res.
4 3 2
HSE HSI MSI LSE
RDYIE RDYIE RDYIE RDYIE
rw rw rw
17 16
Res.
1 0
LSI
RDYIE
rw rw
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