Dma Channel X Memory Address Register (Dma_Cmarx) (X = 1 - ST STM32L4x6 Reference Manual

Direct memory access controller (DMA)
10.5.6

DMA channel x memory address register (DMA_CMARx) (x = 1..7,

where x = channel number)
Address offset: 0x14 + 0d20 × (channel number – 1)
Reset value: 0x0000 0000
This register must not be written when the channel is enabled.
31 30 29
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15 14 13
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Bits 31:0 MA[31:0]: Memory address
Base address of the memory area from/to which the data will be read/written.
When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a half-
word address.
When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word
address.
312/1693
28 27 26 25
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12 11 10 9
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DocID024597 Rev 3
24 23 22 21
MA [31:16]
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8 7 6 5
MA [15:0]
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20 19 18 17
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4 3 2 1
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RM0351
16
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0
rw