ST STM32L4x6 Reference Manual

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Introduction

This reference manual targets application developers. It provides complete information on

how to use the STM32L4x6 microcontroller memory and peripherals.

The STM32L4x6 is a family of microcontrollers with different memory sizes, packages and

peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the

corresponding datasheets.

For information on the ARM

Reference Manual.

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Summary of Contents for ST STM32L4x6

Page 1 This reference manual targets application developers. It provides complete information on how to use the STM32L4x6 microcontroller memory and peripherals. The STM32L4x6 is a family of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics please refer to the corresponding datasheets.
Page 2: Table Of Contents
Contents RM0351 Contents Documentation conventions ....... . . 61 List of abbreviations for registers ....... 61 Glossary .
Page 3 RM0351 Contents 3.3.6 Flash main memory erase sequences ......86 3.3.7 Flash main memory programming sequences ....87 3.3.8 Read-while-write (RWW) .
Page 4 Contents RM0351 4.3.3 Firewall segments ........123 4.3.4 Segment accesses and properties .
Page 5 RM0351 Contents 5.3.9 Standby mode ......... . . 157 5.3.10 Shutdown mode .
Page 6 Contents RM0351 6.2.3 MSI clock ..........187 6.2.4 PLL .
Page 7 RM0351 Contents 6.4.20 APB1 peripheral clock enable register 2 (RCC_APB1ENR2) ..230 6.4.21 APB2 peripheral clock enable register (RCC_APB2ENR) ..232 6.4.22 AHB1 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR) .
Page 8 Contents RM0351 7.4.1 GPIO port mode register (GPIOx_MODER) (x =A..H) ... . . 264 7.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..H) ..264 7.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..H) .
Page 9 RM0351 Contents Connection summary ........286 Interconnection details .
Page 10 Contents RM0351 10.5.1 DMA interrupt status register (DMA_ISR) ..... . 307 10.5.2 DMA interrupt flag clear register (DMA_IFCR) ....308 10.5.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7 , where x = channel number) .
Page 11 RM0351 Contents 12.5.7 Interrupt mask register 2 (EXTI_IMR2) ......332 12.5.8 Event mask register 2 (EXTI_EMR2) ......333 12.5.9 Rising trigger selection register 2 (EXTI_RTSR2) .
Page 12 Contents RM0351 14.6.1 External memory interface signals ......386 14.6.2 NAND Flash supported memories and transactions ....388 14.6.3 Timing diagrams for NAND Flash memory .
Page 13 RM0351 Contents 15.5.8 QUADSPI alternate bytes registers (QUADSPI_ABR) ... . 421 15.5.9 QUADSPI data register (QUADSPI_DR) ..... . . 422 15.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR) .
Page 14 Contents RM0351 16.3.24 End of conversion sequence (EOS, JEOS) ..... 461 16.3.25 Timing diagrams example (single/continuous modes, hardware/software triggers) ....... . . 462 16.3.26 Data management .
Page 15 RM0351 Contents 16.6.1 ADC Common status register (ADCx_CSR) ....532 16.6.2 ADC common control register (ADCx_CCR) ....534 16.6.3 ADC common regular data register for dual mode (ADCx_CDR) .
Page 16 Contents RM0351 17.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) ........564 17.5.10 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) .
Page 17 RM0351 Contents 19.4 COMP low-power modes ........582 19.5 COMP interrupts .
Page 18 Contents RM0351 21.3.6 Parallel data inputs ........616 21.3.7 Channel selection .
Page 19 RM0351 Contents 21.7.11 DFSDM analog watchdog status register (DFSDMx_AWSR) ..645 21.7.12 DFSDM analog watchdog clear flag register (DFSDMx_AWCFR) . . . 645 21.7.13 DFSDM Extremes detector maximum register (DFSDMx_EXMAX) . . 646 21.7.14 DFSDM Extremes detector minimum register (DFSDMx_EXMIN) . . . 646 21.7.15 DFSDM conversion timer register (DFSDMx_CNVTIMR) .
Page 20 Contents RM0351 23.3.4 Charge transfer acquisition sequence ......695 23.3.5 Spread spectrum feature ........696 23.3.6 Max count error .
Page 21 RM0351 Contents 25.3 AES functional description ........716 25.4 Encryption and derivation keys .
Page 22 Contents RM0351 25.14.18 AES register map ......... 749 Advanced-control timers (TIM1/TIM8) .
Page 23 RM0351 Contents 26.4.2 TIM1/TIM8 control register 2 (TIMx_CR2) ..... . 813 26.4.3 TIM1/TIM8 slave mode control register (TIMx_SMCR) ... . 816 26.4.4 TIM1/TIM8 DMA/interrupt enable register (TIMx_DIER) .
Page 24 Contents RM0351 27.3.3 Clock selection ......... . . 871 27.3.4 Capture/compare channels .
Page 25 RM0351 Contents 27.4.18 TIMx DMA address for full transfer (TIMx_DMAR) ....924 27.4.19 TIM2 option register 1 (TIM2_OR1) ......925 27.4.20 TIM3 option register 1 (TIM3_OR1) .
Page 26 Contents RM0351 28.5.5 TIM15 status register (TIM15_SR) ......970 28.5.6 TIM15 event generation register (TIM15_EGR) ....972 28.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1) .
Page 27 RM0351 Contents Basic timers (TIM6/TIM7) ........1010 29.1 TIM6/TIM7 introduction .
Page 28 Contents RM0351 30.4.12 Encoder mode ......... . 1031 30.5 LPTIM low power modes .
Page 29 RM0351 Contents System window watchdog (WWDG) ......1056 33.1 Introduction ..........1056 33.2 WWDG main features .
Page 30 Contents RM0351 34.5 RTC interrupts ......... . . 1080 34.6 RTC registers .
Page 31 RM0351 Contents 35.4.8 I2C master mode ........1128 35.4.9 I2C_TIMINGR register configuration examples .
Page 32 Contents RM0351 36.5.4 USART baud rate generation ......1194 36.5.5 Tolerance of the USART receiver to clock deviation ... . . 1196 36.5.6 USART auto baud rate detection .
Page 33 RM0351 Contents 37.4.1 LPUART character description ......1248 37.4.2 LPUART transmitter ........1251 37.4.3 LPUART receiver .
Page 34 Contents RM0351 38.4.8 Procedure for enabling SPI ....... . 1293 38.4.9 Data transmission and reception procedures .
Page 35 RM0351 Contents 39.4 SAI interrupts ..........1345 39.5 SAI registers .
Page 36 Contents RM0351 40.6.7 SWPMI Transmit data register (SWPMI_TDR) ....1389 40.6.8 SWPMI Receive data register (SWPMI_RDR) ....1390 40.6.9 SWPMI Option register (SWPMI_OR) .
Page 37 RM0351 Contents 41.6.1 SDIO I/O read wait operation by SDMMC_D2 signalling ..1433 41.6.2 SDIO read wait operation by stopping SDMMC_CK ... . . 1434 41.6.3 SDIO suspend/resume operation .
Page 38 Contents RM0351 42.5.1 Silent mode ..........1455 42.5.2 Loop back mode .
Page 39 RM0351 Contents 43.6.1 SRP-capable peripheral ........1502 43.6.2 Peripheral states .
Page 40 Contents RM0351 43.15.12 OTG general core configuration register (OTG_GCCFG) ..1542 43.15.13 OTG core ID register (OTG_CID) ......1543 43.15.14 OTG core LPM configuration register (OTG_GLPMCFG) .
Page 41 RM0351 Contents 43.15.39 OTG device V discharge time register (OTG_DVBUSDIS) ........1570 43.15.40 OTG device V pulsing time register (OTG_DVBUSPULSE) .
Page 42 Using serial wire and releasing the unused debug pins as GPIOs . . 1650 44.5 STM32L4x6 JTAG TAP connection ......1650 44.6 ID codes and locking mechanism .
Page 43 44.17.7 Asynchronous mode ........1675 44.17.8 TRACECLKIN connection inside the STM32L4x6 ....1675 44.17.9 TPIU registers .
Page 44 Table 35. STM32L4x6 peripherals interconnect matrix ........286 Table 36.
Page 45 RM0351 List of tables Table 49. NAND bank selection ........... . 348 Table 50.
Page 46 List of tables RM0351 for master ADC, 0x100 for slave ADC) ........538 Table 101.
Page 47 Table 190. I2C register map and reset values ......... 1176 Table 191. STM32L4x6 USART/UART/LPUART features ....... . 1180 Table 192.
Page 48 Table 205. STM32L4x6 SPI implementation ........
Page 49 RM0351 List of tables Table 250. Response type and SDMMC_RESPx registers ....... 1439 Table 251.
Page 50 STM32L4x6 firewall connection schematics ........122...
Page 51 RM0351 List of figures Figure 49. NAND Flash controller waveforms for common memory access ....389 Figure 50. Access to non ‘CE don’t care’ NAND-Flash ........390 Figure 51.
Page 52 List of figures RM0351 (DISCEN=1, JDISCEN=1) ..........472 Figure 96.
Page 53 RM0351 List of figures Figure 145. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for filtering ............. . . 594 Figure 146.
Page 54 List of figures RM0351 Figure 196. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) ..759 Figure 197. Counter timing diagram, internal clock divided by 1 ......761 Figure 198.
Page 55 RM0351 List of figures Figure 248. Control circuit in external clock mode 2 + trigger mode ......809 Figure 249.
Page 56 List of figures RM0351 Figure 299. TIM16 and TIM17 block diagram ......... . . 933 Figure 300.
Page 57 RM0351 List of figures Figure 346. Encoder mode counting sequence ......... 1033 Figure 347.
Page 58 List of figures RM0351 Figure 398. ISO 7816-3 asynchronous protocol ........1208 Figure 399.
Page 59 RM0351 List of figures Figure 448. Tristate strategy on SD output line on an inactive slot ......1340 Figure 449.
Page 60 List of figures RM0351 Figure 500. Host-mode FIFO address mapping and AHB FIFO access mapping ....1514 Figure 501. Interrupt hierarchy............1517 Figure 502.
Page 61: Documentation Conventions
RM0351 Documentation conventions Documentation conventions List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to these bits. read-only (r) Software can only read these bits. write-only (w) Software can only write to this bit. Reading the bit returns the reset value. read/clear Software can read as well as clear this bit by writing 1.
Page 62: System And Memory Overview
System and memory overview RM0351 System and memory overview System architecture The main system consists of 32-bit multilayer AHB bus matrix that interconnects: • Five masters: ® – Cortex -M4 with FPU core I-bus ® – Cortex -M4 with FPU core D-bus ®...
Page 63: S0: I-Bus
RM0351 System and memory overview Figure 1. System architecture 2.1.1 S0: I-bus ® This bus connects the instruction bus of the Cortex -M4 core to the BusMatrix. This bus is used by the core to fetch instructions. The targets of this bus are the internal Flash memory, SRAM1, SRAM2 and external memories through FMC or QUADSPI.
Page 64: S2: S-Bus
System and memory overview RM0351 2.1.3 S2: S-bus ® This bus connects the system bus of the Cortex -M4 core to the BusMatrix. This bus is used by the core to access data located in a peripheral or SRAM area. The targets of this bus are the SRAM1, the AHB1 peripherals including the APB1 and APB2 peripherals, the AHB2 peripherals and the external memories through the FMC or QUADSPI.
Page 65: Memory Organization
RM0351 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant.
Page 66: Figure 2. Memory Map
RM0351 Figure 2. Memory map It is forbidden to access QUADSPI Flash bank area before having properly configured and enabled the QUADSPI peripheral. 66/1693 DocID024597 Rev 3...
Page 67: Memory Map And Register Boundary Addresses
See the datasheet corresponding to your device for a comprehensive diagram of the memory map. The following table gives the boundary addresses of the peripherals available in the devices. Table 1. STM32L4x6 memory map and peripheral register boundary addresses Boundary address Size (bytes) Peripheral Peripheral register map Section 24.4.4: RNG register...
Page 68 RM0351 Table 1. STM32L4x6 memory map and peripheral register boundary addresses (continued) Boundary address Size (bytes) Peripheral Peripheral register map Section 23.6.11: TSC register 0x4002 4000 - 0x4002 43FF 1 KB 0x4002 3400 - 0x4002 3FFF 1 KB Reserved Section 13.4.6: CRC register...
Page 69 RM0351 Table 1. STM32L4x6 memory map and peripheral register boundary addresses (continued) Boundary address Size (bytes) Peripheral Peripheral register map Section 28.6.20: TIM16&TIM17 0x4001 4800 - 0x4001 4BFF 1 KB TIM17 register map Section 28.6.20: TIM16&TIM17 0x4001 4400 - 0x4001 47FF...
Page 70 RM0351 Table 1. STM32L4x6 memory map and peripheral register boundary addresses (continued) Boundary address Size (bytes) Peripheral Peripheral register map 0x4000 9800 - 0x4000 FFFF 26 KB Reserved Section 30.7.11: LPTIM register 0x4000 9400 - 0x4000 97FF 1 KB LPTIM2...
Page 71: Bit Banding
RM0351 Table 1. STM32L4x6 memory map and peripheral register boundary addresses (continued) Boundary address Size (bytes) Peripheral Peripheral register map Section 36.8.12: USART 0x4000 5000 - 0x4000 53FF 1 KB UART5 register map Section 36.8.12: USART 0x4000 4C00 - 0x4000 4FFF...
Page 72: Embedded Sram
In the STM32L4x6 devices both the peripheral registers and the SRAM1 are mapped to a bit-band region, so that single bit-band write and read operations are allowed. The ®...
Page 73: Sram2 Parity Check
RM0351 2.4.1 SRAM2 Parity check The user can enable the SRAM2 parity check using the option bit SRAM2_PE in the user option byte (refer to Section 3.4.1: Option bytes description). The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in order to increase memory robustness, as required for instance by Class B or SIL norms.
Page 74: Sram2 Read Protection
RM0351 Table 2. SRAM2 organization (continued) Page number Start address End address Page 20 0x1000 5000 0x1000 53FF Page 21 0x1000 5400 0x1000 57FF Page 22 0x1000 5800 0x1000 5BFF Page 23 0x1000 5C00 0x1000 5FFF Page 24 0x1000 6000 0x1000 63FF Page 25 0x1000 6400...
Page 75: Boot Configuration
Embedded Flash memory (FLASH) for more details. Boot configuration In the STM32L4x6, three different boot modes can be selected through the BOOT0 pin and nBOOT1 bit in the User option byte, as shown in the following table. Table 3. Boot modes...
Page 76: Table 4. Memory Mapping Versus Boot Mode/Physical Remap
RM0351 Note: When booting from bank 2, in the application initialization code, you have to relocate the vector table to bank 2 base address. (0x0808 0000) using the NVIC exception table and offset register. Physical remap Once the boot pins are selected, the application software can modify the memory accessible in the code area (in this way the code can be executed through the ICode bus in place of the System bus).
Page 77 2. Even when aliased in the boot memory space, the related memory is still accessible at its original memory space. Embedded boot loader The embedded boot loader is located in the System memory, programmed by ST during production. Refer to AN2606 STM32 microcontroller system memory boot mode. DocID024597 Rev 3...
Page 78: Embedded Flash Memory (Flash)
Embedded Flash memory (FLASH) RM0351 Embedded Flash memory (FLASH) Introduction The Flash memory interface manages CPU AHB ICode and DCode accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. The Flash memory interface accelerates code execution with a system of instruction prefetch and cache lines.
Page 79: Table 5. Flash Module - 1 Mb Dual Bank Organization
USART1, USART2, USART3, USB (DFU), I2C1, I2C2, I2C3, SPI1, SPI2, SPI3. It is programmed by STMicroelectronics when the device is manufactured, and protected against spurious write/erase operations. For further details, please refer to the AN2606 available from www.st.com. – 1 KByte (128 double word) OTP (one-time programmable) bytes for user data.
Page 80: Table 6. Flash Module - 512 Kb Dual Bank Organization
Embedded Flash memory (FLASH) RM0351 Table 5. Flash module - 1 MB dual bank organization (continued) Size Flash area Flash memory addresses Name (bytes) Bank 1 0x1FFF 0000 - 0x1FFF 6FFF 28 K System memory Bank 2 0x1FFF 8000 - 0x1FFF EFFF 28 K Information block Bank 1...
Page 81: Error Code Correction (Ecc)
RM0351 Embedded Flash memory (FLASH) Table 7. Flash module - 256 KB dual bank organization Size Flash area Flash memory addresses Name (bytes) 0x0800 0000 - 0x0800 07FF Page 0 0x0800 0800 - 0x0800 0FFF Page 1 0x0800 1000 - 0x0800 17FF Page 2 0x0800 1800 - 0x0800 1FFF Page 3...
Page 82: Read Access Latency
Embedded Flash memory (FLASH) RM0351 When ECCC or ECCD is set, ADDR_ECC and BK_ECC are not updated if a new ECC error occurs. FLASH_ECCR is updated only when ECC flags are cleared. Note: For a virgin data: 0xFF FFFF FFFF FFFF FFFF, one error is detected and corrected but 2 errors detection is not supported.
Page 83: Adaptive Real-Time Memory Accelerator (Art Accelerator™)
RM0351 Embedded Flash memory (FLASH) Decreasing the CPU frequency: Modify the CPU clock source by writing the SW bits in the RCC_CFGR register If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR Check that the new CPU clock source or/and the new CPU clock prescaler value is/are taken into account by reading the clock source status (SWS bits) or/and the AHB prescaler value (HPRE bits), respectively, in the RCC_CFGR register Program the new number of wait states to the LATENCY bits in...
Page 84: Figure 3. Sequential 16 Bits Instructions Execution
Embedded Flash memory (FLASH) RM0351 Figure 3. Sequential 16 bits instructions execution When the code is not sequential (branch), the instruction may not be present in the currently used instruction line or in the prefetched instruction line. In this case (miss), the penalty in terms of number of cycles is at least equal to the number of wait states.
Page 85: Flash Program And Erase Operations
RM0351 Embedded Flash memory (FLASH) If a loop is present in the current buffer, no new flash access is performed. Instruction cache memory (I-Cache) To limit the time lost due to jumps, it is possible to retain 32 lines of 4*64 bits in an instruction cache memory.This feature can be enabled by setting the instruction cache enable (ICEN) bit in the Flash access control register...
Page 86: Flash Main Memory Erase Sequences
Embedded Flash memory (FLASH) RM0351 write (RWW)). On the contrary, during a program/erase operation to the Flash memory, any attempt to read the same Flash memory bank will stall the bus. The read operation will proceed correctly once the program/erase operation has completed. Unlocking the Flash memory After reset, write is not allowed in the Flash control register (FLASH_CR)
Page 87: Flash Main Memory Programming Sequences
RM0351 Embedded Flash memory (FLASH) Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register Check and clear all error programming flags due to a previous programming. If not, PGSERR is set. Set the MER1 bit or/and MER2 (depending on the bank) in the Flash control register (FLASH_CR).
Page 88 Embedded Flash memory (FLASH) RM0351 automatically when PG bit is set, and disabled automatically when PG bit is cleared, except if the HSI16 is previously enabled with HSION in RCC_CR register. If the user needs to program only one word, double word must be completed with the erase value 0xFFFF FFFF to launch automatically the programming.
Page 89 RM0351 Embedded Flash memory (FLASH) Programming errors Several kind of errors can be detected. In case of error, the Flash operation (programming or erasing) is aborted. • PROGERR: Programming Error In standard programming: PROGERR is set if the word to write is not previously erased (except if the value to program is full zero).
Page 90: Read-While-Write (Rww)
Embedded Flash memory (FLASH) RM0351 In fast programming: FASTERR is set if one of the following conditions occurs: – When FSTPG bit is set for more than 7µs which generates a time-out detection. – When the row fast programming has been interrupted by a MISSERR, PGAERR, WRPERR or SIZERR.
Page 91 RM0351 Embedded Flash memory (FLASH) Check that no Flash memory operation is ongoing by checking the BSY bit in the Flash status register (FLASH_SR) (BSY is active when erase/program operation is on going in bank 1 or bank 2). Set MER1 or MER2 to in the Flash control register (FLASH_CR).
Page 92: Flash Option Bytes
Embedded Flash memory (FLASH) RM0351 FLASH option bytes 3.4.1 Option bytes description The option bytes are configured by the end user depending on the application requirements. As a configuration example, the watchdog may be selected in hardware or software mode (refer to Section 3.4.2: Option bytes programming).
Page 93 WRP2B WRP2B 1FFFF820 Unused Unused Unused Unused _END _STRT _END _STRT User and read protection option bytes Flash memory address: 0x1FFF 7800 ST production value: 0xFFEF F8AA SRAM2 SRAM2 DUAL WWDG IWGD_ IWDG_ IWDG_ Res. Res. Res. Res. Res. Res.
Page 94 0xAA: Level 0, read protection not active 0xCC: Level 2, chip read protection active Others: Level 1, memories read protection active Bank 1 PCROP Start address option bytes Flash memory address: 0x1FFF 7808 ST production value: 0xFFFF FFFF Res. Res. Res. Res.
Page 95 Bits 15:0 PCROP1_STRT: Bank 1 PCROP area start offset PCROP1_STRT contains the first double-word of the bank 1 PCROP area. Bank 1 PCROP End address option bytes Flash memory address: 0x1FFF 7810 ST production value: 0x0000 0000 PCROP Res. Res.
Page 96 Embedded Flash memory (FLASH) RM0351 Bank 1 WRP Area B address option bytes Flash memory address: 0x1FFF 7820 ST production value: 0x0000 00FF Res. Res. Res. Res. Res. Res. Res. Res. WRP1B_END[15:0] Res. Res. Res. Res. Res. Res. Res. Res.
Page 97: Option Bytes Programming
Bits 15:0 PCROP2_END: Bank 2 PCROP area end offset PCROP2_END contains the last double-word of the bank 2 PCROP area. Bank 2 WRP Area A address option bytes Flash memory address: 0x1FFF F818 ST production value: 0x0000 00FF Res. Res. Res.
Page 98 Embedded Flash memory (FLASH) RM0351 unlock this register: Unlock the FLASH_CR with the LOCK clearing sequence (refer to Unlocking the Flash memory). Write OPTKEY1 = 0x08192A3B in the Flash option key register (FLASH_OPTKEYR). Write OPTKEY2 = 0x4C5D6E7F in the FLASH_OPTKEYR register. The user options can be protected against unwanted erase/program operations by setting the OPTLOCK bit by software.
Page 99 RM0351 Embedded Flash memory (FLASH) During option byte loading, the options are read by double word with ECC. If the word and its complement are matching, the option word/byte is copied into the option register. If the comparison between the word and its complement fails, a status bit OPTVERR is set. Mismatch values are forced into the option registers: –...
Page 100: Flash Memory Protection
Embedded Flash memory (FLASH) RM0351 FLASH memory protection The Flash main memory can be protected against external accesses with the Read protection (RDP). The pages of the Flash memory can also be protected against unwanted write due to loss of program counter contexts. The write-protection (WRP) granularity is one page (2 KBytes).
Page 101 RM0351 Embedded Flash memory (FLASH) Level 1: Read protection This is the default protection level when RDP option byte is erased. It is defined as well when RDP value is at any value different from 0xAA and 0xCC, or even if the complement is not correct.
Page 102: Table 12. Access Status Versus Protection Level And Execution Modes
Embedded Flash memory (FLASH) RM0351 Figure 4. Changing the Read protection (RDP) level Table 12. Access status versus protection level and execution modes Debug/ BootFromRam/ User execution (BootFromFlash) Protection BootFromLoader Area level Read Write Erase Read Write Erase Flash main memory System memory...
Page 103: Proprietary Code Readout Protection (Pcrop)
RM0351 Embedded Flash memory (FLASH) 3.5.2 Proprietary code readout protection (PCROP) Apart of the flash memory can be protected against read and write from third parties. The protected area is execute-only: it can only be reached by the STM32 CPU, as an instruction code, while all other accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
Page 104: Write Protection (Wrp)
Embedded Flash memory (FLASH) RM0351 Changing the Read protection level). In this case, PCROP1/2_STRT and PCROP1/2_END are also not erased. Note: It is recommended to align PCROP area with page granularity when using PCROP_RDP, or to leave free the rest of the page where PCROP zone starts or ends. 3.5.3 Write protection (WRP) The user area in Flash memory can be protected against unwanted write operations.
Page 105: Flash Interrupts
RM0351 Embedded Flash memory (FLASH) FLASH interrupts Table 13. Flash interrupt request Event flag/interrupt Interrupt enable control Interrupt event Event flag clearing method End of operation Write EOP=1 EOPIE Operation error OPERR Write OPERR=1 ERRIE Read error RDERR Write RDERR=1 RDERRIE ECC correction ECCC...
Page 106: Flash Registers
Embedded Flash memory (FLASH) RM0351 FLASH registers 3.7.1 Flash access control register (FLASH_ACR) Address offset: 0x00 Reset value: 0x0000 0600 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 107: Flash Power-Down Key Register (Flash_Pdkeyr)
RM0351 Embedded Flash memory (FLASH) Bit 9 ICEN: Instruction cache enable 0: Instruction cache is disabled 1: Instruction cache is enabled Bit 8 PRFTEN: Prefetch enable 0: Prefetch disabled 1: Prefetch enabled Bits 7:3 Reserved, must be kept at reset value. Bits 2:0 LATENCY[2:0]: Latency These bits represent the ratio of the SYSCLK (system clock) period to the Flash access time.
Page 108: Flash Option Key Register (Flash_Optkeyr)
Embedded Flash memory (FLASH) RM0351 KEYR[31:16] KEYR[15:0] Bits 31:0 KEYR: Flash key The following values must be written consecutively to unlock the FLACH_CR register allowing flash programming/erasing operations: KEY1: 0x45670123 KEY2: 0xCDEF89AB 3.7.4 Flash option key register (FLASH_OPTKEYR) Address offset: 0x0C Reset value: 0x0000 0000 Access: no wait state, word access OPTKEYR[31:16]...
Page 109 RM0351 Embedded Flash memory (FLASH) Bits 31:17 Reserved, must be kept at reset value. Bit 16 BSY: Busy This indicates that a Flash operation is in progress. This is set on the beginning of a Flash operation and reset when the operation finishes or when an error occurs.
Page 110: Flash Control Register (Flash_Cr)
Embedded Flash memory (FLASH) RM0351 Bit 3 PROGERR: Programming error Set by hardware when a double-word address to be programmed contains a value different from '0xFFFF FFFF' before programming, except if the data to write is '0x0000 0000'. Cleared by writing 1. Bit 2 Reserved, must be kept at reset value.
Page 111 RM0351 Embedded Flash memory (FLASH) Bit 27 OBL_LAUNCH: Force the option byte loading When set to 1, this bit forces the option byte reloading. This bit is cleared only when the option byte loading is complete. It cannot be written if OPTLOCK is set. 0: Option byte loading complete 1: Option byte loading requested Bit 26 RDERRIE: PCROP read error interrupt enable...
Page 112: Flash Ecc Register (Flash_Eccr)
Embedded Flash memory (FLASH) RM0351 Bits 10:3 PNB[7:0]: Page number selection These bits select the page to erase: If BKER = 0: 00000000: page 0 00000001: page 1 11111111: page 255 If BKER=1 00000000: page 256 00000001: page 257 11111111: page 511 Bit 2 MER1: Bank 1 Mass erase This bit triggers the bank 1 mass erase (all bank 1 user pages) when set.
Page 113: Flash Option Register (Flash_Optr)
RM0351 Embedded Flash memory (FLASH) Bit 24 ECCIE: ECC correction interrupt enable 0: ECCC interrupt disabled 1: ECCC interrupt enabled Bits 23:21 Reserved, must be kept at reset value. Bit 20 SYSF_ECC: System Flash ECC fail This bit indicates that the ECC error correction or double ECC error detection is located in the System Flash.
Page 114: Flash Bank 1 Pcrop Start Address Register (Flash_Pcrop1Sr)
Embedded Flash memory (FLASH) RM0351 Bit 21 DUALBANK: Dual-Bank on 512 KB or 256 KB Flash memory devices 0: 256 KB/512 KB Single-bank Flash: Contiguous addresses in Bank 1 1: 256 KB/512 KB Dual-bank Flash: Refer to Table 6 Table Bit 20 BFB2: Dual-bank boot 0: Dual-bank boot disable 1: Dual-bank boot enable...
Page 115: Flash Bank 1 Pcrop End Address Register (Flash_Pcrop1Er)
RM0351 Embedded Flash memory (FLASH) Access: no wait state when no Flash memory operation is on going, word, half-word access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PCROP1_STRT[15:0] Bits 31:16 Reserved, must be kept cleared Bits 15:0 PCROP1_STRT: Bank 1 PCROP area start offset PCROP1_STRT contains the first double-word of the PCROP area.
Page 116: Flash Bank 1 Wrp Area B Address Register (Flash_Wrp1Br)
Embedded Flash memory (FLASH) RM0351 Res. Res. Res. Res. Res. Res. Res. Res. WRP1A_END[7:0] Res. Res. Res. Res. Res. Res. Res. Res. WRP1A_STRT[7:0] Bits 31:24 Reserved, must be kept cleared Bits 23:16 WRP1A_END: Bank 1 WRP first area “A” end offset WRP1A_END contains the last page of the Bank 1 WRP first area.
Page 117: Flash Bank 2 Pcrop End Address Register (Flash_Pcrop2Er)
RM0351 Embedded Flash memory (FLASH) PCROP2_STRT[15:0] Bits 31:16 Reserved, must be kept cleared Bits 15:0 PCROP2_STRT: Bank 2 PCROP area start offset PCROP2_STRT contains the first double-word of the Bank 2 PCROP area. 3.7.14 Flash Bank 2 PCROP End address register (FLASH_PCROP2ER) Address offset: 0x48 Reset value: 0x0000 XXXX Access: no wait state when no Flash memory operation is on going, word, half-word access...
Page 118: Flash Bank 2 Wrp Area B Address Register (Flash_Wrp2Br)
Embedded Flash memory (FLASH) RM0351 3.7.16 Flash Bank 2 WRP area B address register (FLASH_WRP2BR) Address offset: 0x50 Reset value: 0x00XX 00XX Access: no wait state when no Flash memory operation is on going, word, half-word and byte access Res. Res.
Page 119: Flash Register Map
RM0351 Embedded Flash memory (FLASH) 3.7.17 FLASH register map Table 14. Flash interface - register map and reset values Offset Register LATENCY FLASH_ACR [2:0] 0x00 Reset value FLASH_ PDKEYR[31:0] PDKEYR 0x04 Reset value FLASH_KEYR KEYR[31:0] 0x08 Reset value FLASH_OPT OPTKEYR[31:0] KEYR 0x0C Reset value...
Page 120 Embedded Flash memory (FLASH) RM0351 Table 14. Flash interface - register map and reset values (continued) Offset Register FLASH_ WRP1A_END[7:0] WRP1A_STRT[7:0] WRP1AR 0x2C Reset value X X X X X X X X X X X X X X X X FLASH_ WRP1B_END[7:0] WRP1B_STRT[7:0]...
Page 121: Firewall (Fw)
RM0351 Firewall (FW) Firewall (FW) Introduction The Firewall is made to protect a specific part of code or data into the Non-Volatile Memory, and/or to protect the Volatile data into the SRAM 1 from the rest of the code executed outside the protected area.
Page 122: Firewall Functional Description
The Firewall peripheral is snooping the AMBA buses on which the memories (volatile and non-volatile) are connected. A global architecture view is illustrated in Figure Figure 5. STM32L4x6 firewall connection schematics 4.3.2 Functional requirements There are several requirements to guaranty the highest security level by the application code/data which needs to be protected by the Firewall and to avoid unwanted Firewall alarm (reset generation).
Page 123: Firewall Segments
RM0351 Firewall (FW) end code needs to embed an IAP located in a write protected segment in order to allow future code updates when the production parts will be Level 2 ROP. Write protection In order to offer a maximum security level, the following points need to be respected: •...
Page 124: Segment Accesses And Properties
Firewall (FW) RM0351 Volatile data segment Volatile data used by the protected code located into the code segment must be defined into the SRAM 1 memory. The access to this segment is defined into the Section 4.3.4: Segment accesses and properties.
Page 125: Firewall Initialization
RM0351 Firewall (FW) The Volatile data segment is a bit different from the two others. The segment can be: • Shared (VDS bit in the register) It means that the area and the data located into this segment can be shared between the protected code and the user code executed in a non-protected area.
Page 126: Firewall States
Firewall (FW) RM0351 Below is the initialization procedure to follow: Configure the RCC to enable the clock to the Firewall module Configure the RCC to enable the clock of the system configuration registers Set the base address and length of each segment (CSSA, CSL, NVDSSA, NVDSL, VDSSA, VDSL registers) Set the configuration register of the Firewall (FW_CR register) Enable the Firewall clearing the FWDIS bit in the system configuration register.
Page 127 RM0351 Firewall (FW) Opening the Firewall As soon as the Firewall is enabled, it is closed. It means that most of the accesses to the protected segments are forbidden (refer to Section 4.3.4: Segment accesses and properties). In order to open the Firewall to interact with the protected segments, it is mandatory to apply the “call gate”...
Page 128: Firewall Registers
Firewall (FW) RM0351 Firewall registers 4.4.1 Code segment start address (FW_CSSA) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. ADD[23:16] ADD[15:8] Bits 31:24 Reserved, must be kept at reset value. Bits 23:8 ADD[23:8]: code segment start address The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a 256-byte granularity.
Page 129: Non-Volatile Data Segment Start Address (Fw_Nvdssa)
RM0351 Firewall (FW) 4.4.3 Non-volatile data segment start address (FW_NVDSSA) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. ADD[23:16] ADD[15:8] Bits 31:24 Reserved, must be kept at the reset value. Bits 23:8 ADD[23:8]: Non-volatile data segment start address The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a 256-byte granularity.
Page 130: Volatile Data Segment Start Address (Fw_Vdssa)
Firewall (FW) RM0351 4.4.5 Volatile data segment start address (FW_VDSSA) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. [16] ADD[15:6] Bits 31:17 Reserved, must be kept at the reset value. Bits 16:6 ADD[16:6]: Volatile data segment start address The LSB bits of the start address (bit 5:0) are reserved and forced to 0 in order to allow a 64-byte granularity.
Page 131: Configuration Register (Fw_Cr)
RM0351 Firewall (FW) 4.4.7 Configuration register (FW_CR) Address offset: 0x20 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 132: Firewall Register Map
Firewall (FW) RM0351 4.4.8 Firewall register map The table below provides the Firewall register map and reset values. Table 17. Firewall register map and reset values Offset Register FW_CSSA Reset Value FW_CSL LENG Reset Value FW_NVDSSA Reset Value FW_NVDSL LENG Reset Value FW_VDSSA 0x10...
Page 133: Power Control (Pwr)
RM0351 Power control (PWR) Power control (PWR) Power supplies The STM32L4x devices require a 1.71 V to 3.6 V V operating voltage supply. Several independent supplies (V ), can be provided for specific DDIO2 DDUSB peripherals: • = 1.71 V to 3.6 V is the external power supply for the I/Os, the internal regulator and the system analog such as reset, power management and internal clocks.
Page 134: Independent Analog Peripherals Supply
Power control (PWR) RM0351 When the VREF+ is double-bonded with VDDA in a package, the internal voltage reference buffer is not available and must be kept disable (refer to datasheet for packages pinout description). must always be equal to V REF- An embedded linear voltage regulator is used to supply the internal digital power V CORE...
Page 135: Independent I/O Supply Rail
RM0351 Power control (PWR) The V supply can be monitored by the Peripheral Voltage Monitoring, and compared with two thresholds (1.65 V for PVM3 or 2.2 V for PVM4), refer to Section 5.2.3: Peripheral Voltage Monitoring (PVM) for more details. When a single supply is used, V can be externally connected to V through the...
Page 136: Independent Lcd Supply
Power control (PWR) RM0351 5.1.4 Independent LCD supply The VLCD pin is provided to control the contrast of the glass LCD. This pin can be used in two ways: • It can receive from an external circuitry the desired maximum voltage that is provided on segment and common lines to the glass LCD by the microcontroller.
Page 137: Voltage Regulator
RM0351 Power control (PWR) Note: Due to the fact that the analog switch can transfer only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g.
Page 138: Dynamic Voltage Scaling Management
Power control (PWR) RM0351 contents of the registers and internal SRAM1 and SRAM2. • In Stop 1 and Stop 2 modes, the main regulator is off and the low-power regulator (LPR) supplies low power to the V domain, preserving the contents of the CORE registers and of internal SRAM1 and SRAM2.
Page 139: Power Supply Supervisor
RM0351 Power control (PWR) Power supply supervisor 5.2.1 Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) The device has an integrated power-on reset (POR) / power-down reset (PDR), coupled with a brown-out reset (BOR) circuitry. The BOR is active in all power modes except Shutdown mode, and cannot be disabled.
Page 140: Peripheral Voltage Monitoring (Pvm)
Power control (PWR) RM0351 Figure 9. PVD thresholds 5.2.3 Peripheral Voltage Monitoring (PVM) Only V is monitored by default, as it is the only supply required for all system-related functions. The other supplies (V and V ) can be independent from V DDIO2 DDUSB and can be monitored with four Peripheral Voltage Monitoring (PVM).
Page 141: Low-Power Modes
RM0351 Power control (PWR) can be enabled to confirm whether the supply is present or not. The following sequence must be done before using the USB_OTG peripheral: If V is independent from V DDUSB Enable the PVM1 by setting PVME1 bit in the Power control register 2 (PWR_CR2).
Page 142 Power control (PWR) RM0351 regulator is in low-power mode to minimize the regulator's operating current. Refer to Section 5.3.2: Low-power run mode (LP run). ® • Low-power sleep mode: This mode is entered from the Low-power run mode: Cortex M4 is off. Refer to Section 5.3.5: Low-power sleep mode (LP sleep).
Page 143: Figure 10. Low-Power Modes Possible Transitions
RM0351 Power control (PWR) Figure 10. Low-power modes possible transitions DocID024597 Rev 3 143/1693...
Page 144: Table 19. Low-Power Mode Summary
Power control (PWR) RM0351 Table 19. Low-power mode summary Voltage Wakeup Wakeup regulators Mode name Entry Effect on clocks source system clock WFI or Return Sleep CPU clock OFF Same as before Any interrupt from ISR entering Sleep (Sleep-now or no effect on other clocks mode Sleep-on-exit)
Page 145: Table 20. Functionalities Depending On The Working Mode
RM0351 Power control (PWR) Table 20. Functionalities depending on the working mode Stop 0/1 Stop 2 Standby Shutdown Low- Low- Peripheral Sleep power power VBAT sleep Flash memory (up to 1 MB) SRAM1 (up to 96 KB) SRAM2 (32 KB) FSMC QUADSPI Backup Registers...
Page 146 Power control (PWR) RM0351 Table 20. Functionalities depending on the working mode (continued) Stop 0/1 Stop 2 Standby Shutdown Low- Low- Peripheral Sleep power power VBAT sleep I2Cx (x=1,2) I2C3 SPIx (x=1,2,3) SDMMC1 SWPMI SAIx (x=1,2) DFSDM ADCx (x=1,2,3) DACx (x=1,2) VREFBUF OPAMPx (x=1,2) COMPx (x=1,2)
Page 147: Run Mode
RM0351 Power control (PWR) Table 20. Functionalities depending on the working mode (continued) Stop 0/1 Stop 2 Standby Shutdown Low- Low- Peripheral Sleep power power VBAT sleep CRC calculation unit (11) GPIOs pins (10) (10) 1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not available. 2.
Page 148: Low-Power Run Mode (Lp Run)
Power control (PWR) RM0351 Peripheral clock gating In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped at any time to reduce the power consumption. To further reduce the power consumption in Sleep mode, the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.
Page 149: Low Power Modes
RM0351 Power control (PWR) Table 21. Low-power run Low-power run mode Description LPR = 0 Mode exit Wait until REGLPF = 0 Increase the system clock frequency Wakeup latency Regulator wakeup time from low-power mode 5.3.3 Low power modes Entering low power mode Low power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or ®...
Page 150: Sleep Mode
-M4 System Control register. If WFI or return from ISR was used for entry Interrupt: refer to Table 42: STM32L4x6 vector table If WFE was used for entry and SEVONPEND = 0: Wakeup event: refer to Section 12.3.2: Wakeup event management...
Page 151: Stop 0 Mode
-M4 System Control register. If WFI or Return from ISR was used for entry Interrupt: refer to Table 42: STM32L4x6 vector table If WFE was used for entry and SEVONPEND = 0: Wakeup event: refer to Section 12.3.2: Wakeup event management...
Page 152 Power control (PWR) RM0351 HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx (x=1,2,3), U(S)ARTx(x=1,2...5) and LPUART) can switch on the HSI16 to receive a frame, and switch off the HSI16 after receiving the frame if it is not a wakeup frame. In this case, the HSI16 clock is propagated only to the peripheral requesting it.
Page 153: Stop 1 Mode
Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer to Table 42: STM32L4x6 vector table. If WFE was used for entry and SEVONPEND = 0: Any EXTI Line configured in event mode.
Page 154: Stop 2 Mode
Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer to Table 42: STM32L4x6 vector table. If WFE was used for entry and SEVONPEND = 0: Any EXTI Line configured in event mode.
Page 155 RM0351 Power control (PWR) I/O states in Stop 2 mode In the Stop 2 mode, all I/O pins keep the same state as in the Run mode. Entering Stop 2 mode The Stop 2 mode is entered according Section : Entering low power mode, when the ®...
Page 156: Table 26. Stop 2 Mode
Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). The interrupt source can be external interrupts or peripherals with wakeup capability. Refer to Table 42: STM32L4x6 vector table. If WFE was used for entry and SEVONPEND = 0: Any EXTI Line configured in event mode.
Page 157: Standby Mode
RM0351 Power control (PWR) 5.3.9 Standby mode The Standby mode allows to achieve the lowest power consumption with BOR. It is based ® on the Cortex -M4 deepsleep mode, with the voltage regulators disabled (except when SRAM2 content is preserved). The PLL, the HSI16, the MSI and the HSE oscillators are also switched off.
Page 158: Table 27. Standby Mode
Power control (PWR) RM0351 Table 27. Standby mode Standby mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® – SLEEPDEEP bit is set in Cortex -M4 System Control register – No interrupt (for WFI) or event (for WFE) is pending –...
Page 159: Shutdown Mode
RM0351 Power control (PWR) 5.3.10 Shutdown mode The Shutdown mode allows to achieve the lowest power consumption. It is based on the deepsleep mode, with the voltage regulator disabled. The V domain is consequently CORE powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also switched off.
Page 160: Auto-Wakeup From Low-Power Mode
Power control (PWR) RM0351 Table 28. Shutdown mode Shutdown mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: ® – SLEEPDEEP bit is set in Cortex -M4 System Control register – No interrupt (for WFI) or event (for WFE) is pending –...
Page 161: Pwr Registers
RM0351 Power control (PWR) PWR registers The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 5.4.1 Power control register 1 (PWR_CR1) Address offset: 0x00 Reset value: 0x0000 0200. This register is reset after wakeup from Standby mode. Res.
Page 162: Power Control Register 2 (Pwr_Cr2)
Power control (PWR) RM0351 5.4.2 Power control register 2 (PWR_CR2) Address offset: 0x04 Reset value: 0x0000 0000. This register is reset when exiting the Standby mode. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 163: Power Control Register 3 (Pwr_Cr3)
RM0351 Power control (PWR) Bit 4 PVME1: Peripheral voltage monitoring 1 enable: vs. 1.2V DDUSB 0: PVM1 ( monitoring vs. 1.2V threshold) disable. DDUSB 1: PVM1 ( monitoring vs. 1.2V threshold) enable. DDUSB Bits 3:1 PLS[2:0]: Power voltage detector level selection. These bits select the voltage threshold detected by the power voltage detector: 000: V around 2.0 V...
Page 164: Power Control Register 4 (Pwr_Cr4)
Power control (PWR) RM0351 Bit 10 APC: Apply pull-up and pull-down configuration When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and PWR_PDCRx registers are not applied to the I/Os.
Page 165: Power Status Register 1 (Pwr_Sr1)
RM0351 Power control (PWR) Bits 31:10 Reserved, must be kept at reset value. Bit 9 VBRS: V battery charging resistor selection 0: Charge V through a 5 kOhms resistor 1: Charge V through a 1.5 kOhms resistor Bit 8 VBE: V battery charging enable 0: V battery charging disable...
Page 166: Power Status Register 2 (Pwr_Sr2)
Power control (PWR) RM0351 Bits 31:16 Reserved, must be kept at reset value. Bit 15 WUFI: Wakeup flag internal This bit is set when a wakeup is detected on the internal wakeup line. It is cleared when all internal wakeup sources are cleared. Bits 14:9 Reserved, must be kept at reset value.
Page 167 RM0351 Power control (PWR) Bits 31:16 Reserved, must be kept at reset value. Bit 15 PVMO4: Peripheral voltage monitoring output: V vs. 2.2 V 0: V voltage is above PVM4 threshold (around 2.2 V). 1: V voltage is below PVM4 threshold (around 2.2 V). Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0).
Page 168: Power Status Clear Register (Pwr_Scr)
Power control (PWR) RM0351 5.4.7 Power status clear register (PWR_SCR) Address offset: 0x18 Reset value: 0x0000 0000. Access: 3 additional APB cycles are needed to write this register vs. a standard APB write. Res. Res. Res. Res. Res. Res. Res. Res.
Page 169: Power Port A Pull-Down Control Register (Pwr_Pdcra)
RM0351 Power control (PWR) Bits 31:16 Reserved, must be kept at reset value. Bit 15 PU15: Port A pull-up bit 15 When set, this bit activates the pull-up on PA[15] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PD15 bit is also set. Bit 14 Reserved, must be kept at reset value.
Page 170: Power Port B Pull-Down Control Register (Pwr_Pdcrb)
Power control (PWR) RM0351 PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port B pull-up bit y (y=0..15) When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.
Page 171: Power Port C Pull-Down Control Register (Pwr_Pdcrc)
RM0351 Power control (PWR) PU15 PU14 PU13 PU12 PU11 PU10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port C pull-up bit y (y=0..15) When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set.
Page 172: Power Port D Pull-Down Control Register (Pwr_Pdcrd)
Power control (PWR) RM0351 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PUy: Port D pull-up bit y (y=0..15) When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register. The pull-up is not activated if the corresponding PDy bit is also set. 5.4.15 Power Port D pull-down control register (PWR_PDCRD) Address offset: 0x3C.
Page 173: Power Port E Pull-Down Control Register (Pwr_Pdcre)
RM0351 Power control (PWR) 5.4.17 Power Port E pull-down control register (PWR_PDCRE) Address offset: 0x44. Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with PWRRST bit in the RCC_APB1RSTR1 register. Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read).
Page 174: Power Port G Pull-Up Control Register (Pwr_Pucrg)
Power control (PWR) RM0351 Access: Additional APB cycles are needed to access this register vs. a standard APB access (3 for a write and 2 for a read). Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 175: Power Port H Pull-Up Control Register (Pwr_Pucrh)
RM0351 Power control (PWR) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PD15 PD14 PD13 PD12 PD11 PD10 Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 PDy: Port G pull-down bit y (y=0..15) When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register.
Page 176 Power control (PWR) RM0351 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:2 Reserved, must be kept at reset value. Bits 1:0 PDy: Port H pull-down bit y (y=0..1) When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register. 176/1693 DocID024597 Rev 3...
Page 177: Pwr Register Map And Reset Value Table
RM0351 Power control (PWR) 5.4.24 PWR register map and reset value table Table 29. PWR register map and reset values Offset Register LPMS PWR_CR1 [1:0] [2:0] 0x000 Reset value PWR_CR2 PLS [2:0] 0x004 Reset value PWR_CR3 0x008 Reset value PWR_CR4 0x00C Reset value PWR_SR1...
Page 178 Power control (PWR) RM0351 Table 29. PWR register map and reset values (continued) Offset Register PWR_PDCRE 0x044 Reset value PWR_PUCRF 0x048 Reset value PWR_PDCRF 0x04C Reset value PWR_PUCRG 0x050 Reset value PWR_PDCRG 0x054 Reset value PWR_PUCRH 0x058 Reset value PWR_PDCRH 0x05C Reset value Refer...
Page 179: Reset And Clock Control (Rcc)
RM0351 Reset and clock control (RCC) Reset and clock control (RCC) Reset There are three types of reset, defined as system reset, power reset and backup domain reset. 6.1.1 Power reset A power reset is generated when one of the following events occurs: a Brown-out reset (BOR).
Page 180: Backup Domain Reset
Reset and clock control (RCC) RM0351 Figure 11. Simplified diagram of the reset circuit Software reset ® The SYSRESETREQ bit in Cortex -M4 Application Interrupt and Reset Control Register must be set to force a software reset on the device (refer to the STM32F3xx/F4xx/L4xx ®...
Page 181: Clocks
RM0351 Reset and clock control (RCC) Software reset, triggered by setting the BDRST bit in the Backup domain control register (RCC_BDCR). or V power on, if both supplies have previously been powered off. A backup domain reset only affects the LSE oscillator, the RTC, the Backup registers and the RCC Backup domain control register.
Page 182 Reset and clock control (RCC) RM0351 All the peripheral clocks are derived from their bus clock (HCLK, PCLK1 or PCLK2) except: • The 48 MHz clock, used for USB OTG FS, SDMMC and RNG. This clock is derived (selected by software) from one of the three following sources: –...
Page 183 RM0351 Reset and clock control (RCC) – APB1 clock (PCLK1) – External clock mapped on LPTIMx_IN1 The functionality in Stop mode (including wakeup) is supported only when the clock is LSI or LSE, or in external clock mode. • The RTC and LCD clock which is derived (selected by software) from one of the three following sources: –...
Page 184: Figure 12. Clock Tree
Reset and clock control (RCC) RM0351 Figure 12. Clock tree 1. For full details about the internal and external clock source characteristics, please refer to the “Electrical 184/1693 DocID024597 Rev 3...
Page 185: Hse Clock
RM0351 Reset and clock control (RCC) characteristics” section in your device datasheet. 2. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4). When the programmable factor is ‘1’, the AHB prescaler must be equal to ‘1’. 6.2.1 HSE clock The high speed external clock signal (HSE) can be generated from two possible clock...
Page 186: Hsi16 Clock
Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1 % accuracy at T =25°C. After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the...
Page 187: Msi Clock
The MSI RC oscillator frequency can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1 % accuracy at an ambient temperature, TA, of 25 °C. After reset, the factory calibration value is loaded in the...
Page 188: Lse Clock
Reset and clock control (RCC) RM0351 6.2.4 The device embeds 3 PLLs: PLL, PLLSAI1, PLLSAI2. Each PLL provides up to three independent outputs. The internal PLLs can be used to multiply the HSI16, HSE or MSI output clock frequency. The PLLs input frequency must be between 4 and 16 MHz. The selected clock source is divided by a programmable factor PLLM from 1 to 8 to provide a clock frequency in the requested input range.
Page 189: Lsi Clock
RM0351 Reset and clock control (RCC) capability (LSEDRV=00) when the LSE is ON. However, once LSEDRV is selected, the drive capability can not be increased if LSEON=1. The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware.
Page 190: Table 30. Clock Source Frequency
Reset and clock control (RCC) RM0351 Table 30. Clock source frequency Clock frequency Product voltage range HSI16 PLL/PLLSAI1/PLLSAI2 80 MHz Range 1 48 MHz 16 MHz 48 MHz (VCO max = 344 MHz) 26 MHz Range 2 24 MHz range 16 MHz 26 MHz (VCO max = 128 MHz)
Page 191: Adc Clock
RM0351 Reset and clock control (RCC) 6.2.11 ADC clock The ADC clock is derived from the system clock, or from the PLLSAI1 or the PLLSAI2 output. It can reach 80 MHz and can be divided by the following prescalers values: 1,2,4,6,8,10,12,16,32,64,128 or 256 by configuring the ADC123_CCR register.
Page 192: Figure 14. Frequency Measurement With Tim15 In Capture Mode
Reset and clock control (RCC) RM0351 6.2.15 Clock-out capability • The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin. One of seven clock signals can be selected as the MCO clock. – –...
Page 193: Figure 15. Frequency Measurement With Tim16 In Capture Mode
RM0351 Reset and clock control (RCC) The input capture channel of the Timer 15 can be a GPIO line or an internal clock of the MCU. This selection is performed through the TI1_RMP bit in the TIM15_OR register. The possibilities are the following ones: •...
Page 194 Reset and clock control (RCC) RM0351 The input capture channel of the Timer 17 can be a GPIO line or an internal clock of the MCU. This selection is performed through the TI1_RMP[1:0] bits in the TIM17_OR register. The possibilities are the following ones: •...
Page 195: Low-Power Modes
RM0351 Reset and clock control (RCC) 6.2.17 Peripheral clock enable register (RCC_AHBxENR, RCC_APBxENRy) Each peripheral clock can be enabled by the xxxxEN bit of the RCC_AHBxENR, RCC_APBxENRy registers. When the peripheral clock is not active, the peripheral registers read or write accesses are not supported.
Page 196: Clock Control Register (Rcc_Cr)
Reset and clock control (RCC) RM0351 RCC registers 6.4.1 Clock control register (RCC_CR) Address offset: 0x00 Reset value: 0x0000 0063. HSEBYP is not affected by reset. Access: no wait state, word, half-word and byte access Res. Res. SAI2 SAI2 SAI1 SAI1 PLLON Res.
Page 197 RM0351 Reset and clock control (RCC) Bits 23:20 Reserved, must be kept at reset value. Bit 19 CSSON: Clock security system enable Set by software to enable the clock security system. When CSSON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE clock failure is detected.
Page 198 Reset and clock control (RCC) RM0351 Bit 8 HSION: HSI clock enable Set and cleared by software. Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the HSI16 oscillator ON when STOPWUCK=1 or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE crystal oscillator.
Page 199: Internal Clock Sources Calibration Register (Rcc_Icscr)
RM0351 Reset and clock control (RCC) Bit 0 MSION: MSI clock enable This bit is set and cleared by software. Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode. Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop modes, or in case of a failure of the HSE oscillator Set by hardware when used directly or indirectly as system clock.
Page 200: Clock Configuration Register (Rcc_Cfgr)
Reset and clock control (RCC) RM0351 6.4.3 Clock configuration register (RCC_CFGR) Address offset: 0x08 Reset value: 0x0000 0000 Access: 0 ≤ wait state ≤ 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during clock source switch. From 0 to 15 wait states inserted if the access occurs when the APB or AHB prescalers values update is on going.
Page 201 RM0351 Reset and clock control (RCC) STOPWUCK: Wakeup from Stop and CSS backup clock selection Bit 15 Set and cleared by software to select the system clock used when exiting Stop mode. The selected clock is also used as emergency clock for the Clock Security System on HSE. Warning: STOPWUCK must not be modified when the Clock Security System is enabled by HSECSSON in RCC_CR register and the system clock is HSE (SWS=”10”) or a switch on HSE is requested (SW=”10”).
Page 202 Reset and clock control (RCC) RM0351 Bits 1:0 SW[1:0]: System clock switch Set and cleared by software to select system clock source (SYSCLK). Configured by HW to force MSI oscillator selection when exiting Standby or Shutdown mode. Configured by HW to force MSI or HSI16 oscillator selection when exiting Stop mode or in case of failure of the HSE oscillator, depending on STOPWUCK value.
Page 203: Pll Configuration Register (Rcc_Pllcfgr)
RM0351 Reset and clock control (RCC) 6.4.4 PLL configuration register (RCC_PLLCFGR) Address offset: 0x0C Reset value: 0x0000 1000 Access: no wait state, word, half-word and byte access This register is used to configure the PLL clock outputs according to the formulas: •...
Page 204 Reset and clock control (RCC) RM0351 Bits 22:21 PLLQ[1:0]: Main PLL division factor for PLL48M1CLK (48 MHz clock). Set and cleared by software to control the frequency of the main PLL output clock PLL48M1CLK. This output can be selected for USB, RNG, SDMMC (48 MHz clock). These bits can be written only if PLL is disabled.
Page 205 RM0351 Reset and clock control (RCC) Bits 14:8 PLLN[6:0]: Main PLL multiplication factor for VCO Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled. VCO output frequency = VCO input frequency x PLLN with 8 =< PLLN =< 86 0000000: PLLN = 0 wrong configuration 0000001: PLLN = 1 wrong configuration 0000111: PLLN = 7 wrong configuration...
Page 206: Pllsai1 Configuration Register (Rcc_Pllsai1Cfgr)
Reset and clock control (RCC) RM0351 6.4.5 PLLSAI1 configuration register (RCC_PLLSAI1CFGR) Address offset: 0x10 Reset value: 0x0000 1000 Access: no wait state, word, half-word and byte access This register is used to configure the PLLSAI1 clock outputs according to the formulas: •...
Page 207 RM0351 Reset and clock control (RCC) Bits 22:21 PLLSAI1Q[1:0]: SAI1PLL division factor for PLL48M2CLK (48 MHz clock) Set and cleared by software to control the frequency of the SAI1PLL output clock PLL48M2CLK. This output can be selected for USB, RNG, SDMMC (48 MHz clock). These bits can be written only if SAI1PLL is disabled.
Page 208 Reset and clock control (RCC) RM0351 Bit 15 Reserved, must be kept at reset value. Bits 14:8 PLLSAI1N[6:0]: SAI1PLL multiplication factor for VCO Set and cleared by software to control the multiplication factor of the VCO. These bits can be written only when the SAI1PLL is disabled.
Page 209: Pllsai2 Configuration Register (Rcc_Pllsai2Cfgr)
RM0351 Reset and clock control (RCC) 6.4.6 PLLSAI2 configuration register (RCC_PLLSAI2CFGR) Address offset: 0x14 Reset value: 0x0000 1000 Access: no wait state, word, half-word and byte access This register is used to configure the PLLSAI2 clock outputs according to the formulas: •...
Page 210 Reset and clock control (RCC) RM0351 Bit 16 PLLSAI2PEN: SAI2PLL PLLSAI2CLK output enable Set and reset by software to enable the PLLSAI2CLK output of the SAI2PLL. In order to save power, when the PLLSAI2CLK output of the SAI2PLL is not used, the value of PLLSAI2PEN should be 0.
Page 211: Clock Interrupt Enable Register (Rcc_Cier)
RM0351 Reset and clock control (RCC) 6.4.7 Clock interrupt enable register (RCC_CIER) Address offset: 0x18 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 212 Reset and clock control (RCC) RM0351 Bit 2 MSIRDYIE: MSI ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the MSI oscillator stabilization. 0: MSI ready interrupt disabled 1: MSI ready interrupt enabled Bit 1 LSERDYIE: LSE ready interrupt enable Set and cleared by software to enable/disable interrupt caused by the LSE oscillator stabilization.
Page 213: Clock Interrupt Flag Register (Rcc_Cifr)
RM0351 Reset and clock control (RCC) 6.4.8 Clock interrupt flag register (RCC_CIFR) Address offset: 0x1C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 214 Reset and clock control (RCC) RM0351 Bit 3 HSIRDYF: HSI16 ready interrupt flag Set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in a response to setting the HSION (refer to Clock control register (RCC_CR)). When HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit is not set and no interrupt is generated.
Page 215: Clock Interrupt Clear Register (Rcc_Cicr)
RM0351 Reset and clock control (RCC) 6.4.9 Clock interrupt clear register (RCC_CICR) Address offset: 0x20 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 216: Ahb1 Peripheral Reset Register (Rcc_Ahb1Rstr)
Reset and clock control (RCC) RM0351 Bit 2 MSIRDYC: MSI ready interrupt clear This bit is set by software to clear the MSIRDYF flag. 0: No effect 1: MSIRDYF cleared Bit 1 LSERDYC: LSE ready interrupt clear This bit is set by software to clear the LSERDYF flag. 0: No effect 1: LSERDYF cleared Bit 0 LSIRDYC: LSI ready interrupt clear...
Page 217: Ahb2 Peripheral Reset Register (Rcc_Ahb2Rstr)
RM0351 Reset and clock control (RCC) Bits 7:2 Reserved, must be kept at reset value. Bit 1 DMA2RST: DMA2 reset Set and cleared by software. 0: No effect 1: Reset DMA2 Bit 0 DMA1RST: DMA1 reset Set and cleared by software. 0: No effect 1: Reset DMA1 6.4.11...
Page 218: Ahb3 Peripheral Reset Register (Rcc_Ahb3Rstr)
Reset and clock control (RCC) RM0351 Bit 7 GPIOHRST: IO port H reset Set and cleared by software. 0: No effect 1: Reset IO port H Bit 6 GPIOGRST: IO port G reset Set and cleared by software. 0: No effect 1: Reset IO port G Bit 5 GPIOFRST: IO port F reset Set and cleared by software.
Page 219 RM0351 Reset and clock control (RCC) Bits 31:9 Reserved, must be kept at reset value. Bit 8 QSPIRST: Quad SPI memory interface reset Set and cleared by software. 0: No effect 1: Reset QUADSPI Bits 7:1 Reserved, must be kept at reset value. Bit 0 FMCRST: Flexible memory controller reset Set and cleared by software.
Page 220: Apb1 Peripheral Reset Register 1 (Rcc_Apb1Rstr1)
Reset and clock control (RCC) RM0351 6.4.13 APB1 peripheral reset register 1 (RCC_APB1RSTR1) Address offset: 0x38 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access DAC1 CAN1 I2C2 I2C1 UART5 UART4 USART3 USART2 LPTIM1 OPAMP I2C3R Res.
Page 221 RM0351 Reset and clock control (RCC) Bit 21 I2C1RST: I2C1 reset Set and cleared by software. 0: No effect 1: Reset I2C1 Bit 20 UART5RST: UART5 reset Set and cleared by software. 0: No effect 1: Reset UART5 Bit 19 UART4RST: UART4 reset Set and cleared by software.
Page 222: Apb1 Peripheral Reset Register 2 (Rcc_Apb1Rstr2)
Reset and clock control (RCC) RM0351 Bit 3 TIM5RST: TIM5 timer reset Set and cleared by software. 0: No effect 1: Reset TIM5 Bit 2 TIM4RST: TIM3 timer reset Set and cleared by software. 0: No effect 1: Reset TIM3 Bit 1 TIM3RST: TIM3 timer reset Set and cleared by software.
Page 223: Apb2 Peripheral Reset Register (Rcc_Apb2Rstr)
RM0351 Reset and clock control (RCC) 6.4.15 APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x40 Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access DFSDM SAI2 SAI1 TIM17 TIM16 TIM15R Res. Res. Res. Res. Res. Res. Res.
Page 224: Ahb1 Peripheral Clock Enable Register (Rcc_Ahb1Enr)
Reset and clock control (RCC) RM0351 Bit 14 USART1RST: USART1 reset Set and cleared by software. 0: No effect 1: Reset USART1 Bit 13 TIM8RST: TIM8 timer reset Set and cleared by software. 0: No effect 1: Reset TIM8 timer Bit 12 SPI1RST: SPI1 reset Set and cleared by software.
Page 225: Ahb2 Peripheral Clock Enable Register (Rcc_Ahb2Enr)
RM0351 Reset and clock control (RCC) Bits 31:17 Reserved, must be kept at reset value. Bit 16 TSCEN: Touch Sensing Controller clock enable Set and cleared by software. 0: TSC clock disable 1: TSC clock enable Bits 15:13 Reserved, must be kept at reset value. Bit 12 CRCEN: CRC clock enable Set and cleared by software.
Page 226 Reset and clock control (RCC) RM0351 Bits 31:19 Reserved, must be kept at reset value. Bit 18 RNGEN: Random Number Generator clock enable Set and cleared by software. 0: Random Number Generator clock disabled 1: Random Number Generator clock enabled Bit 17 Reserved, must be kept at reset value.
Page 227: Ahb3 Peripheral Clock Enable Register(Rcc_Ahb3Enr)
RM0351 Reset and clock control (RCC) Bit 2 GPIOCEN: IO port C clock enable Set and cleared by software. 0: IO port C clock disabled 1: IO port C clock enabled Bit 1 GPIOBEN: IO port B clock enable Set and cleared by software. 0: IO port B clock disabled 1: IO port B clock enabled Bit 0 GPIOAEN: IO port A clock enable...
Page 228 Reset and clock control (RCC) RM0351 Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported. LPTIM1 OPAMP DAC1 CAN1 I2C3 I2C2 I2C1 UART5 UART4 USART3 USART2 Res. Res. Res. Res. TIM7 SPI3 SPI2 TIM2...
Page 229 RM0351 Reset and clock control (RCC) Bit 20 UART5EN: UART5 clock enable Set and cleared by software. 0: UART5 clock disabled 1: UART5 clock enabled Bit 19 UART4EN: UART4 clock enable Set and cleared by software. 0: UART4 clock disabled 1: UART4 clock enabled Bit 18 USART3EN: USART3 clock enable Set and cleared by software.
Page 230: Apb1 Peripheral Clock Enable Register 2 (Rcc_Apb1Enr2)
Reset and clock control (RCC) RM0351 Bit 3 TIM5EN: TIM5 timer clock enable Set and cleared by software. 0: TIM5 clock disabled 1: TIM5 clock enabled Bit 2 TIM4EN: TIM4 timer clock enable Set and cleared by software. 0: TIM4 clock disabled 1: TIM4 clock enabled Bit 1 TIM3EN: TIM3 timer clock enable Set and cleared by software.
Page 231 RM0351 Reset and clock control (RCC) Bit 2 SWPMI1EN: Single wire protocol clock enable Set and cleared by software. 0: SWPMI1 clock disable 1: SWPMI1 clock enable Bit 1 Reserved, must be kept at reset value. Bit 0 LPUART1EN: Low power UART 1 clock enable Set and cleared by software.
Page 232: Apb2 Peripheral Clock Enable Register (Rcc_Apb2Enr)
Reset and clock control (RCC) RM0351 6.4.21 APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x60 Reset value: 0x0000 0000 Access: word, half-word and byte access Note: When the peripheral clock is not active, the peripheral registers read or write access is not supported.
Page 233 RM0351 Reset and clock control (RCC) Bit 14 USART1EN: USART1clock enable Set and cleared by software. 0: USART1clock disabled 1: USART1clock enabled Bit 13 TIM8EN: TIM8 timer clock enable Set and cleared by software. 0: TIM8 timer clock disabled 1: TIM8 timer clock enabled Bit 12 SPI1EN: SPI1 clock enable Set and cleared by software.
Page 234 Reset and clock control (RCC) RM0351 Bits 31:17 Reserved, must be kept at reset value. Bit 16 TSCSMEN: Touch Sensing Controller clocks enable during Sleep and Stop modes Set and cleared by software. 0: TSC clocks disabled by the clock gating during Sleep and Stop modes 1: TSC clocks enabled by the clock gating during Sleep and Stop modes...
Page 235 RM0351 Reset and clock control (RCC) OTGFS SRAM2 GPIOH GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Res. Res. Res. Res. Res. SMEN SMEN SMEN SMEN SMEN SMEN SMEN SMEN SMEN SMEN SMEN Bits 31:19 Reserved, must be kept at reset value. Bit 18 RNGSMEN: Random Number Generator clocks enable during Sleep and Stop modes Set and cleared by software.
Page 236 Reset and clock control (RCC) RM0351 Bit 4 GPIOESMEN: IO port E clocks enable during Sleep and Stop modes Set and cleared by software. 0: IO port E clocks disabled by the clock gating during Sleep and Stop modes 1: IO port E clocks enabled by the clock gating during Sleep and Stop modes Bit 3 GPIODSMEN: IO port D clocks enable during Sleep and Stop modes Set and cleared by software.
Page 237: Apb1 Peripheral Clocks Enable In Sleep And Stop Modes Register
RM0351 Reset and clock control (RCC) Bit 8 QSPISMEN Quad SPI memory interface clocks enable during Sleep and Stop modes Set and cleared by software. 0: QUADSPI clocks disabled by the clock gating during Sleep and Stop modes 1: QUADSPI clocks enabled by the clock gating during Sleep and Stop modes Bits 7:1 Reserved, must be kept at reset value.
Page 238 Reset and clock control (RCC) RM0351 Bit 25 CAN1SMEN: CAN1 clocks enable during Sleep and Stop modes Set and cleared by software. 0: CAN1 clocks disabled by the clock gating during Sleep and Stop modes 1: CAN1 clocks enabled by the clock gating during Sleep and Stop modes Bit 24 Reserved, must be kept at reset value.
Page 239 RM0351 Reset and clock control (RCC) Bit 11 WWDGSMEN: Window watchdog clocks enable during Sleep and Stop modes Set and cleared by software. This bit is forced to ‘1’ by hardware when the hardware WWDG option is activated. 0: Window watchdog clocks disabled by the clock gating during Sleep and Stop modes 1: Window watchdog clocks enabled by the clock gating during Sleep and Stop modes...
Page 240 Reset and clock control (RCC) RM0351 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPTIM Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UART1 2SMEN SMEN SMEN Bits 31:6 Reserved, must be kept at reset value.
Page 241 RM0351 Reset and clock control (RCC) 6.4.27 APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR) Address: 0x80 Reset value: 0x0167 7C01 Access: word, half-word and byte access DFSDM SAI2 SAI1 TIM17 TIM16 TIM15 Res. Res. Res. Res. Res.
Page 242 Reset and clock control (RCC) RM0351 Bit 14 USART1SMEN: USART1clocks enable during Sleep and Stop modes Set and cleared by software. 0: USART1clocks disabled by the clock gating during Sleep and Stop modes 1: USART1clocks enabled by the clock gating during Sleep and Stop modes Bit 13 TIM8SMEN: TIM8 timer clocks enable during Sleep and Stop modes Set and cleared by software.
Page 243: Peripherals Independent Clock Configuration Register (Rcc_Ccipr)
RM0351 Reset and clock control (RCC) 6.4.28 Peripherals independent clock configuration register (RCC_CCIPR) Address: 0x88 Reset value: 0x0000 0000 Access: no wait states, word, half-word and byte access DFSDM ADCSEL[1:0] CLK48SEL[1:0] SAI2SEL[1:0] SAI1SEL[1:0] LPTIM2SEL[1:0] LPTIM1SEL[1:0 I2C3SEL[1:0] LPUART1SEL UART5SEL UART4SEL USART3SEL USART2SEL USART1SEL I2C2SEL[1:0]...
Page 244 Reset and clock control (RCC) RM0351 Bits 23:22 SAI1SEL[1:0]: SAI1 clock source selection These bits are set and cleared by software to select the SAI1 clock source. 00: PLLSAI1 “P” clock (PLLSAI1CLK) selected as SAI1 clock 01: PLLSAI2 “P” clock (PLLSAI2CLK) selected as SAI1 clock 10: PLL “P”...
Page 245 RM0351 Reset and clock control (RCC) Bits 9:8 UART5SEL[1:0]: UART5 clock source selection These bits are set and cleared by software to select the UART5 clock source. 00: PCLK selected as UART5 clock 01: System clock (SYSCLK) selected as UART5 clock 10: HSI16 clock selected as UART5 clock 11: LSE clock selected as UART5 clock Bits 7:6 UART4SEL[1:0]: UART4 clock source selection...
Page 246: Backup Domain Control Register (Rcc_Bdcr)
Reset and clock control (RCC) RM0351 6.4.29 Backup domain control register (RCC_BDCR) Address offset: 0x90 Reset value: 0x0000 0000, reset by Backup domain Reset, except LSCOSEL, LSCOEN and BDRST which are reset only by Backup domain power-on reset. Access: 0 ≤wait state ≤3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register.
Page 247 RM0351 Reset and clock control (RCC) Bits 9:8 RTCSEL[1:0]: RTC clock source selection Set by software to select the clock source for the RTC. Once the RTC clock source has been selected, it cannot be changed anymore unless the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is set).
Page 248: Control/Status Register (Rcc_Csr)
Reset and clock control (RCC) RM0351 6.4.30 Control/status register (RCC_CSR) Address: 0x94 Reset value: 0x0C00 0600, reset by system Reset, except reset flags by power Reset only. Access: 0 ≤ wait state ≤ 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. LPWR WWDG IWWG...
Page 249 RM0351 Reset and clock control (RCC) Bit 25 OBLRSTF: Option byte loader reset flag Set by hardware when a reset from the Option Byte loading occurs. Cleared by writing to the RMVF bit. 0: No reset from Option Byte loading occurred 1: Reset from Option Byte loading occurred Bit 24 FWRSTF: Firewall reset flag Set by hardware when a reset from the firewall occurs.
Page 250: Table 31. Rcc Register Map And Reset Values
Reset and clock control (RCC) RM0351 6.4.31 RCC register map The following table gives the RCC register map and the reset values. Table 31. RCC register map and reset values Off- Register MSIRANGE RCC_CR [3:0] 0x00 Reset value RCC_ICSCR HSITRIM[4:0] HSICAL[7:0] MSITRIM[7:0] MSICAL[7:0]...
Page 251 RM0351 Reset and clock control (RCC) Table 31. RCC register map and reset values (continued) Off- Register RCC_ AHB1RSTR 0x28 Reset value RCC_ AHB2RSTR 0x2C Reset value RCC_ AHB3RSTR 0x30 Reset value RCC_ APB1RSTR1 0x38 Reset value RCC_ APB1RSTR2 0x3C Reset value RCC_ APB2RSTR...
Page 252 Reset and clock control (RCC) RM0351 Table 31. RCC register map and reset values (continued) Off- Register RCC_ APB1ENR2 0x5C Reset value RCC_ APB2ENR 0x60 Reset value RCC_ AHB1SMENR 0x68 Reset value RCC_ AHB2SMENR 0x6C Reset value RCC_ AHB3SMENR 0x70 Reset value RCC_ APB1SM...
Page 253 RM0351 Reset and clock control (RCC) Table 31. RCC register map and reset values (continued) Off- Register RCC_BDCR 0x90 [1:0] [1:0] Reset value MSIS RCC_CSR RANGE[3:0] 0x94 Reset value DocID024597 Rev 3 253/1693...
Page 254: Introduction
General-purpose I/Os (GPIO) RM0351 General-purpose I/Os (GPIO) Introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL).
Page 255: Figure 17. Basic Structure Of An I/O Port Bit
RM0351 General-purpose I/Os (GPIO) Figure 17 Figure 18 show the basic structures of a standard and a 5 V tolerant I/O port bit, respectively. Table 32 gives the possible port bit configurations. Figure 17. Basic structure of an I/O port bit Figure 18.
Page 256: Table 32. Port Bit Configuration Table
General-purpose I/Os (GPIO) RM0351 Table 32. Port bit configuration table MODE(i) OSPEED(i) PUPD(i) OTYPER(i) I/O configuration [1:0] [1:0] [1:0] GP output GP output PP + PU GP output PP + PD Reserved SPEED [1:0] GP output GP output OD + PU GP output OD + PD Reserved (GP output OD)
Page 257: General-Purpose I/O (Gpio)
RM0351 General-purpose I/Os (GPIO) 7.3.1 General-purpose I/O (GPIO) During and just after reset, the alternate functions are not active and most of the I/O ports are configured in analog mode. The debug pins are in AF pull-up/pull-down after reset: • PA15: JTDI in pull-up •...
Page 258: I/O Port Control Registers
General-purpose I/Os (GPIO) RM0351 – For the ADC, DAC, OPAMP, and COMP, configure the desired I/O in analog mode in the GPIOx_MODER register and configure the required function in the ADC, DAC, OPAMP, and COMP registers. For the ADC, it is necessary to configure the GPIOx_ASCR register.
Page 259: Gpio Locking Mechanism
RM0351 General-purpose I/Os (GPIO) 7.3.6 GPIO locking mechanism It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the same).
Page 260: Figure 19. Input Floating/Pull Up/Pull Down Configurations
General-purpose I/Os (GPIO) RM0351 Figure 19. Input floating/pull up/pull down configurations 7.3.10 Output configuration When the I/O port is programmed as output: • The output buffer is enabled: – Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated) –...
Page 261: Figure 20. Output Configuration
RM0351 General-purpose I/Os (GPIO) Figure 20. Output configuration 7.3.11 Alternate function configuration When the I/O port is programmed as alternate function: • The output buffer can be configured in open-drain or push-pull mode • The output buffer is driven by the signals coming from the peripheral (transmitter enable and data) •...
Page 262: Figure 21. Alternate Function Configuration
General-purpose I/Os (GPIO) RM0351 Figure 21. Alternate function configuration 7.3.12 Analog configuration When the I/O port is programmed as analog configuration: • The output buffer is disabled • The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin.
Page 263: Using The Hse Or Lse Oscillator Pins As Gpios
RM0351 General-purpose I/Os (GPIO) 7.3.13 Using the HSE or LSE oscillator pins as GPIOs When the HSE or LSE oscillator is switched OFF (default state after reset), the related oscillator pins can be used as normal GPIOs. When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the RCC_CSR register) the oscillator takes control of its associated pins and the GPIO configuration of these pins has no effect.
Page 264: Gpio Registers
General-purpose I/Os (GPIO) RM0351 GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table The peripheral registers can be written in word, half word or byte mode. 7.4.1 GPIO port mode register (GPIOx_MODER) (x =A..H) Address offset:0x00...
Page 265 RM0351 General-purpose I/Os (GPIO) 7.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..H) Address offset: 0x08 Reset value: • 0x0C00 0000 for port A • 0x0000 0000 for the other ports OSPEED15 OSPEED14 OSPEED13 OSPEED12 OSPEED11 OSPEED10 OSPEED9 OSPEED8 [1:0] [1:0] [1:0]...
Page 266: Gpio Port Input Data Register (Gpiox_Idr) (X = A..h)
General-purpose I/Os (GPIO) RM0351 7.4.5 GPIO port input data register (GPIOx_IDR) (x = A..H) Address offset: 0x10 Reset value: 0x0000 XXXX (where X means undefined) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 267 RM0351 General-purpose I/Os (GPIO) Bits 31:16 BRy: Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODx bit 1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority.
Page 268 General-purpose I/Os (GPIO) RM0351 Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active.
Page 269: Gpio Port Bit Reset Register (Gpiox_Brr) (X =A..h)
RM0351 General-purpose I/Os (GPIO) 7.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..H) Address offset: 0x24 Reset value: 0x0000 0000 AFSEL15[3:0] AFSEL14[3:0] AFSEL13[3:0] AFSEL12[3:0] AFSEL11[3:0] AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0] Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: 1000: AF8...
Page 270 General-purpose I/Os (GPIO) RM0351 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ASC15 ASC14 ASC13 ASC12 ASC11 ASC10 ASC9 ASC8 ASC7 ASC6 ASC5 ASC4 ASC3 ASC2 ASC1 ASC0 Bits 31:16 Reserved Bits 15:0 ASCy: Port x analog switch control y (y= 0..15) These bits are written by software to configure the analog connection of the IOs 0: Disconnect analog switch to the ADC input (reset state) 1: Connect analog switch to the ADC input...
Page 271: Table 33. Gpio Register Map And Reset Values
RM0351 General-purpose I/Os (GPIO) 7.4.13 GPIO register map The following table gives the GPIO register map and reset values. Table 33. GPIO register map and reset values Offset Register GPIOA_MODER 0x00 Reset value GPIOB_MODER 0x00 Reset value GPIOx_MODER (where x = C..H) 0x00 Reset value GPIOx_OTYPER...
Page 272 General-purpose I/Os (GPIO) RM0351 Table 33. GPIO register map and reset values (continued) Offset Register GPIOx_BSRR (where x = A..H) 0x18 Reset value GPIOx_LCKR (where x = A..H) 0x1C Reset value GPIOx_AFRL AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0] (where x = A..H) 0x20 Reset value...
Page 273: Syscfg Main Features
RM0351 System configuration controller (SYSCFG) System configuration controller (SYSCFG) SYSCFG main features The STM32L4x6 devices feature a set of configuration registers. The main purposes of the system configuration controller are the following: • Remapping memory areas • Managing the external interrupt line connection to the GPIOs •...
Page 274: Syscfg Configuration Register 1 (Syscfg_Cfgr1)
System configuration controller (SYSCFG) RM0351 Bit 8 FB_MODE: Flash Bank mode selection 0: Flash Bank 1 mapped at 0x0800 0000 (and aliased @0x0000 0000) and Flash Bank 2 mapped at 0x0808 0000 (and aliased at 0x0008 0000) 1: Flash Bank2 mapped at 0x0800 0000 (and aliased @0x0000 0000) and Flash Bank 1 mapped at 0x0808 0000 (and aliased at 0x0008 0000) Bits 7:3 Reserved, must be kept at reset value.
Page 275 RM0351 System configuration controller (SYSCFG) Bits 31:26 FPU_IE[5..0]: Floating Point Unit interrupts enable bits FPU_IE[5]: Inexact interrupt enable FPU_IE[4]: Input denormal interrupt enable FPU_IE[3]: Overflow interrupt enable FPU_IE[2]: underflow interrupt enable FPU_IE[1]: Divide-by-zero interrupt enable FPU_IE[0]: Invalid operation interrupt enable Bits 25:23 Reserved, must be kept at reset value.
Page 276: Syscfg External Interrupt Configuration Register
System configuration controller (SYSCFG) RM0351 Bit 8 BOOSTEN: I/O analog switch voltage booster enable 0: I/O analog switches are supplied by V voltage. This is the recommended configuration when using the ADC in high V voltage operation. 1: I/O analog switches are supplied by a dedicated voltage booster (supplied by V ).
Page 277 RM0351 System configuration controller (SYSCFG) Bits 10:8 EXTI2[2:0]: EXTI 2 configuration bits These bits are written by software to select the source input for the EXTI2 external interrupt. 000: PA[2] pin 001: PB[2] pin 010: PC[2] pin 011: PD[2] pin 100: PE[2] pin 101: PF[2] pin 110: PG[2] pin...
Page 278: Syscfg External Interrupt Configuration Register
System configuration controller (SYSCFG) RM0351 8.2.4 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) Address offset: 0x0C Reset value: 0x0000 0000 EXTI7[2:0] EXTI6[2:0] EXTI5[2:0] EXTI4[2:0] Bits 31:15 Reserved, must be kept at reset value. Bits 14:12 EXTI7[2:0]: EXTI 7 configuration bits These bits are written by software to select the source input for the EXTI7 external interrupt.
Page 279: Syscfg External Interrupt Configuration Register
RM0351 System configuration controller (SYSCFG) Bits 6:4 EXTI5[2:0]: EXTI 5 configuration bits These bits are written by software to select the source input for the EXTI5 external interrupt. 000: PA[5] pin 001: PB[5] pin 010: PC[5] pin 011: PD[5] pin 100: PE[5] pin 101: PF[5] pin 110: PG[5] pin...
Page 280 System configuration controller (SYSCFG) RM0351 Bits 31:15 Reserved, must be kept at reset value. Bits 14:12 EXTI11[2:0]: EXTI 11 configuration bits These bits are written by software to select the source input for the EXTI11 external interrupt. 000: PA[11] pin 001: PB[11] pin 010: PC[11] pin 011: PD[11] pin...
Page 281 RM0351 System configuration controller (SYSCFG) 8.2.6 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x14 Reset value: 0x0000 0000 EXTI15[2:0] EXTI14[2:0] EXTI13[2:0] EXTI12[2:0] Bits 31:15 Reserved, must be kept at reset value. Bits 14:12 EXTI15[2:0]: EXTI15 configuration bits These bits are written by software to select the source input for the EXTI15 external interrupt.
Page 282: Syscfg Sram2 Control And Status Register (Syscfg_Scsr)
System configuration controller (SYSCFG) RM0351 Bits 6:4 EXTI13[2:0]: EXTI13 configuration bits These bits are written by software to select the source input for the EXTI13 external interrupt. 000: PA[13] pin 001: PB[13] pin 010: PC[13] pin 011: PD[13] pin 100: PE[13] pin 101: PF[13] pin 110: PG[13] pin 111: Reserved...
Page 283: Syscfg Configuration Register 2 (Syscfg_Cfgr2)
RM0351 System configuration controller (SYSCFG) 8.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2) Address offset: 0x1C System reset value: 0x0000 0000 ECCL PVDL rc_w1 Bits 31:9 Reserved, must be kept at reset value Bit 8 SPF: SRAM2 parity error flag This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing ‘1’.
Page 284: Syscfg Sram2 Key Register (Syscfg_Skr)
System configuration controller (SYSCFG) RM0351 System reset value: 0x0000 0000 P31WP P30WP P29WP P28WP P27WP P26WP P25WP P24WP P23WP P22WP P21WP P20WP P19WP P18WP P17WP P16WP P15WP P14WP P13WP P12WP P11WP P10WP P9WP P8WP P7WP P6WP P5WP P4WP P3WP P2WP P1WP P0WP Bits 31:0 PxWP (x= 0 to 31): SRAM2 page x write protection...
Page 285: Table 34. Syscfg Register Map And Reset Values
RM0351 System configuration controller (SYSCFG) 8.2.11 SYSCFG register map The following table gives the SYSCFG register map and the reset values. Table 34. SYSCFG register map and reset values Offset Register SYSCFG_ MEM_ MODE MEMRMP 0x00 Reset value SYSCFG_CFGR1 FPU_IE[5..0] 0x04 Reset value EXTI3...
Page 286: Table 35. Stm32L4X6 Peripherals Interconnect Matrix
In addition, these hardware connections remove software latency and allow design of predictable system. Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes. Connection summary (1) (2) Table 35. STM32L4x6 peripherals interconnect matrix Destination Source TIM1 TIM8 TIM2...
Page 287: Interconnection Details
RM0351 Peripherals interconnect matrix (1) (2) Table 35. STM32L4x6 peripherals interconnect matrix (continued) Destination Source VREFINT OPAMP1 12 12 OPAMP2 12 12 DAC1 12 12 12 12 DAC2 12 12 EXTI COMP1 13 13 13 13 13 13 13 8...
Page 288 Peripherals interconnect matrix RM0351 The modes of synchronization are detailed in: • Section 26.3.26: Timer synchronization for advanced-control timers (TIM1/TIM8) • Section 27.3.18: Timers and external trigger synchronization for general-purpose timers (TIM2/TIM3/TIM4/TIM5) • Section 28.4.17: External trigger synchronization (TIM15 only) for general-purpose timer (TIM15) Triggering signals...
Page 289: From Adc (Adc1/Adc2/Adc3) To Timer (Tim1/Tim8)
RM0351 Peripherals interconnect matrix 9.3.3 From ADC (ADC1/ADC2/ADC3) to timer (TIM1/TIM8) Purpose ADC1/ADC2/ADC3 can provide trigger event through watchdog signals to advanced-control timers (TIM1/TIM8). A description of the ADC analog watchdog setting is provided in: Section 16.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx).
Page 290: From Dfsdm To Timer (Tim1/Tim8/Tim15/Tim16/Tim17)
Peripherals interconnect matrix RM0351 Triggering signals The output (from timer) is on signal TIMx_TRGO/TIMx_TRGO2 or TIM16_OC1. The input (on DFSDM) is on signal DFSDM_INTRG[0:8]. The connection between timers, EXTI and DFSDM is provided in Table 122: DFSDM triggers connection. Active power mode Run, Sleep, Low-power run, Low-power sleep.
Page 291: From Rtc, Comp1, Comp2 To Low-Power Timer (Lptim1/Lptim2)
RM0351 Peripherals interconnect matrix External clock LSE can be used as input to general-purpose timers (TIM2) on TIM2_ETR pin, see Section 27.4.19: TIM2 option register 1 (TIM2_OR1). Active power mode Run, Sleep, Low-power run, Low-power sleep. 9.3.8 From RTC, COMP1, COMP2 to low-power timer (LPTIM1/LPTIM2) Purpose RTC alarm A/B, RTC_TAMP1/2/3 input detection, COMP1/2_OUT can be used as trigger to start LPTIM counters (LPTIM1/2).
Page 292: From Usb To Timer (Tim2)
Peripherals interconnect matrix RM0351 A description of dual ADC mode is provided in: Section 16.3.30: Dual ADC modes. Triggering signals Internal to the ADCs. Active power mode Run, Sleep, Low-power run, Low-power sleep. 9.3.11 From USB to timer (TIM2) Purpose USB (OTG_FS SOF) can generate a trigger to general-purpose timer (TIM2).
Page 293: From System Errors To Timers (Tim1/Tim8/Tim15/Tim16/Tim17)
RM0351 Peripherals interconnect matrix 9.3.13 From comparators (COMP1/COMP2) to timers (TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17) Purpose Comparators (COMP1/COMP2) output values can be connected to timers (TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17) input captures or TIMx_ETR signals. The connection to ETR is described in Section 26.3.4: External trigger input. Comparators (COMP1/COMP2) output values can also generate break input signals for timers (TIM1/TIM8) on input pins TIMx_BKIN or TIMx_BKIN2 through GPIO alternate function selection using open drain connection of IO, see Section 26.3.17: Bidirectional...
Page 294: From Timers (Tim16/Tim17) To Irtim
Peripherals interconnect matrix RM0351 9.3.15 From timers (TIM16/TIM17) to IRTIM Purpose General-purpose timer (TIM16/TIM17) output channel TIMx_OC1 are used to generate the waveform of infrared signal output. The functionality is described in Section 31: Infrared interface (IRTIM). Active power mode Run, Sleep, Low-power run, Low-power sleep.
Page 295: Introduction
RM0351 Direct memory access controller (DMA) Direct memory access controller (DMA) 10.1 Introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions.
Page 296: Table 36. Dma Implementation
Direct memory access controller (DMA) RM0351 The block diagram is shown in the following figure. Figure 23. DMA block diagram 10.3 DMA implementation This manual describes the full set of features implemented in DMA1. DMA2 supports the same number of channels, and is identical to DMA1. Table 36.
Page 297: Dma Functional Description
RM0351 Direct memory access controller (DMA) 10.4 DMA functional description The DMA controller performs direct memory transfer by sharing the system bus with the ® Cortex -M4 core. The DMA request may stop the CPU access to the system bus for some bus cycles, when the CPU and DMA are targeting the same destination (memory or peripheral).
Page 298: Dma Channels
Direct memory access controller (DMA) RM0351 10.4.3 DMA channels Each channel can handle DMA transfer between a peripheral register located at a fixed address and a memory address. The amount of data to be transferred (up to 65535) is programmable. The register which contains the amount of data items to be transferred is decremented after each transaction.
Page 299: Table 37. Programmable Data Width & Endian Behavior (When Bits Pinc = Minc = 1)
RM0351 Direct memory access controller (DMA) Once half of the bytes are transferred, the half-transfer flag (HTIF) is set and an interrupt is generated if the Half-Transfer Interrupt Enable bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag (TCIF) is set and an interrupt is generated if the Transfer Complete Interrupt Enable bit (TCIE) is set.
Page 300 Direct memory access controller (DMA) RM0351 Table 37. Programmable data width & endian behavior (when bits PINC = MINC = 1) (continued) Number Source of data Destination Destination Source content: port items to Transfer operations content: port width address / data width transfer address / data...
Page 301: Table 38. Dma Interrupt Requests
RM0351 Direct memory access controller (DMA) Addressing an AHB peripheral that does not support byte or halfword write operations When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does not support byte or halfword write operations (when HSIZE is not used by the peripheral) and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two examples below:...
Page 302: Dma Request Mapping
Direct memory access controller (DMA) RM0351 10.4.7 DMA request mapping DMA controller The hardware requests from the peripherals (TIM1/2/3/4/5/6/7/8/15/16/17, ADC1/2/3, DAC1/2, SPI1/2/3, I2C1/2/3, SDMMC1, QUADSPI, SWPMI1, DFSDM, SAI1/2, AES, USART1/2/3, UART4/5 and LPUART1) are mapped to the DMA1 or DMA2 channels (1 to 7) through the DMA1/2 channel selection register.
Page 303: Figure 24. Dma1 Request Mapping
RM0351 Direct memory access controller (DMA) Figure 24. DMA1 request mapping DocID024597 Rev 3 303/1693...
Page 304: Figure 25. Dma2 Request Mapping
Direct memory access controller (DMA) RM0351 Figure 25. DMA2 request mapping 304/1693 DocID024597 Rev 3...
Page 305: Table 39. Summary Of The Dma1 Requests For Each Channel
RM0351 Direct memory access controller (DMA) Table 39. Summary of the DMA1 requests for each channel Request. Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 number ADC1 ADC2 ADC3 DFSDM0 DFSDM1 DFSDM2 DFSDM3 SPI1_RX SPI1_TX SPI2_RX SPI2_TX...
Page 306: Table 40. Summary Of The Dma2 Requests For Each Channel
Direct memory access controller (DMA) RM0351 Table 40. Summary of the DMA2 requests for each channel Request. Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 number ADC1 ADC2 ADC3 SAI1_A SAI1_B SAI2_A SAI2_B SAI1_A SAI1_B UART5_TX UART5_RX...
Page 307: Dma Registers
RM0351 Direct memory access controller (DMA) 10.5 DMA registers Refer to Section 1.1 on page 61 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32- bit). 10.5.1 DMA interrupt status register (DMA_ISR) Address offset: 0x00...
Page 308: Dma Interrupt Flag Clear Register (Dma_Ifcr)
Direct memory access controller (DMA) RM0351 10.5.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 CTEIF CHTIF Res. Res. Res. Res. CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 CGIF5 CTEIF CHTIF CTCIF CTEIF CHTIF CGIF4 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1...
Page 309 RM0351 Direct memory access controller (DMA) 10.5.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7 , where x = channel number) Address offset: 0x08 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 Res. Res. Res. Res. Res.
Page 310 Direct memory access controller (DMA) RM0351 Bit 5 CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory Bit 3 TEIE: Transfer error interrupt enable...
Page 311: Dma Channel X Number Of Data Register (Dma_Cndtrx) (X = 1
RM0351 Direct memory access controller (DMA) 10.5.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number) Address offset: 0x0C + 0d20 × (channel number – 1) Reset value: 0x0000 0000 Res. Res. Res. Res.
Page 312: Dma Channel X Memory Address Register (Dma_Cmarx) (X = 1
Direct memory access controller (DMA) RM0351 10.5.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number) Address offset: 0x14 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. MA [31:16] MA [15:0] Bits 31:0 MA[31:0]: Memory address...
Page 313: Dma1 Channel Selection Register (Dma1_Cselr)
RM0351 Direct memory access controller (DMA) 10.5.7 DMA1 channel selection register (DMA1_CSELR) Address offset: 0xA8 (with respect to DMA1 base address) Reset value: 0x0000 0000 This register is used to manage the mapping of DMA channels (see Figure 24). Res. Res.
Page 314 Direct memory access controller (DMA) RM0351 Bits 15:12 C4S[3:0]: DMA channel 4 selection 0000: Channel 4 mapped on DFSDM0 0001: Channel 4 mapped on SPI2_RX 0010: Channel 4 mapped on USART1_TX 0011: Channel 4 mapped on I2C2_TX 0100: Reserved 0101: Channel 4 mapped on TIM7_UP/DAC2 0110: Channel 4 mapped on TIM4_CH2 0111: Channel 4 mapped on TIM1_CH4/TIM1_TRIG/TIM1_COM others: Reserved...
Page 315: Dma2 Channel Selection Register (Dma2_Cselr)
RM0351 Direct memory access controller (DMA) 10.5.8 DMA2 channel selection register (DMA2_CSELR) Address offset: 0xA8 (with respect to DMA2 base address) Reset value: 0x0000 0000 This register is used to manage the mapping of DMA channels (see Figure 25). Res. Res.
Page 316 Direct memory access controller (DMA) RM0351 Bits 15:12 C4S[3:0]: DMA channel 4 selection 0000: Channel 4 mapped on ADC2 0001: Channel 4 mapped on SAI2_B 0010: Reserved 0011: Channel 4 mapped on TIM6_UP/DAC1 0100: Channel 4 mapped on SPI1_TX 0101: Channel 4 mapped on TIM5_CH2 0110: Reserved 0111: Channel 4 mapped on SDMMC1 others: Reserved...
Page 317: Table 41. Dma Register Map And Reset Values
RM0351 Direct memory access controller (DMA) 10.5.9 DMA register map The following table gives the DMA register map and the reset values. Table 41. DMA register map and reset values Offset Register DMA_ISR 0x00 Reset value DMA_IFCR 0x04 Reset value DMA_CCR1 [1:0] 0x08...
Page 318 Direct memory access controller (DMA) RM0351 Table 41. DMA register map and reset values (continued) Offset Register DMA_CPAR4 PA[31:0] 0x4C Reset value DMA_CMAR4 MA[31:0] 0x50 Reset value 0x54 Reserved DMA_CCR5 [1:0] 0x58 Reset value DMA_CNDTR5 NDT[15:0] 0x5C Reset value DMA_CPAR5 PA[31:0] 0x60 Reset value...
Page 319: Nvic Main Features
RM0351 Nested vectored interrupt controller (NVIC) Nested vectored interrupt controller (NVIC) 11.1 NVIC main features ® • 82 maskable interrupt channels (not including the sixteen Cortex -M4 with FPU interrupt lines) • 16 programmable priority levels (4 bits of interrupt priority are used) •...
Page 320: Table 42. Stm32L4X6 Vector Table
Nested vectored interrupt controller (NVIC) RM0351 11.3 Interrupt and exception vectors Table 42. STM32L4x6 vector table Type of Acronym Description Address priority Reserved 0x0000 0000 fixed Reset Reset 0x0000 0004 Non maskable interrupt. The RCC Clock fixed Security System (CSS) is linked to the NMI 0x0000 0008 vector.
Page 321 RM0351 Nested vectored interrupt controller (NVIC) Table 42. STM32L4x6 vector table (continued) Type of Acronym Description Address priority settable DMA1_CH4 DMA1 channel 4 interrupt 0x0000 0078 settable DMA1_CH5 DMA1 channel 5 interrupt 0x0000 007C settable DMA1_CH6 DMA1 channel 6 interrupt...
Page 322 Nested vectored interrupt controller (NVIC) RM0351 Table 42. STM32L4x6 vector table (continued) Type of Acronym Description Address priority settable TIM1_CC TIM8 capture compare interrupt 0x0000 00F8 settable ADC3 ADC3 global interrupt 0x0000 00FC settable FMC global interrupt 0x0000 0100 settable...
Page 323 RM0351 Nested vectored interrupt controller (NVIC) Table 42. STM32L4x6 vector table (continued) Type of Acronym Description Address priority settable TSC global interrupt 0x0000 0174 settable LCD global interrupt 0x0000 0178 settable AES global interrupt 0x0000 017C settable RNG global interrupt...
Page 324: Introduction
Extended interrupts and events controller (EXTI) RM0351 Extended interrupts and events controller (EXTI) 12.1 Introduction The EXTI main features are as follows: • Generation of up to 40 event/interrupt requests – 26 configurable lines – 14 direct lines • Independent mask on each event/interrupt line •...
Page 325: Figure 26. Configurable Interrupt/Event Block Diagram
Figure 26. Configurable interrupt/event block diagram 12.3.2 Wakeup event management The STM32L4x6 is able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated either by: • enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex -M4 System Control register.
Page 326: Peripherals Asynchronous Interrupts
Configure the corresponding mask bit (EXTI_IMR, EXTI_EMR). Set the required bit of the software interrupt register (EXTI_SWIER). 12.4 EXTI interrupt/event line mapping In the STM32L4x6, 40 interrupt/event lines are available. The GPIOs are connected to 16 configurable interrupt/event lines (see Figure 27).
Page 327: Table 43. Exti Lines Connections
RM0351 Extended interrupts and events controller (EXTI) Figure 27. External interrupt/event GPIO mapping The 40 lines are connected as shown in Table 43: EXTI lines connections. Table 43. EXTI lines connections EXTI line Line source Line type 0-15 GPIO configurable configurable OTG_FS wakeup event direct...
Page 328 Extended interrupts and events controller (EXTI) RM0351 Table 43. EXTI lines connections (continued) EXTI line Line source Line type I2C2 wakeup direct I2C3 wakeup direct USART1 wakeup direct USART2 wakeup direct USART3 wakeup direct UART4 wakeup direct UART5 wakeup direct LPUART1 wakeup direct LPTIM1...
Page 329: Interrupt Mask Register 1 (Exti_Imr1)
RM0351 Extended interrupts and events controller (EXTI) 12.5 registers EXTI Refer to Section 1.1 on page 61 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 12.5.1 Interrupt mask register 1 (EXTI_IMR1) Address offset: 0x00 Reset value: 0xFF82 0000 IM31...
Page 330: Rising Trigger Selection Register 1 (Exti_Rtsr1)
Extended interrupts and events controller (EXTI) RM0351 12.5.3 Rising trigger selection register 1 (EXTI_RTSR1) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. RT22 RT21 RT20 RT19 RT18 Res. RT16 RT15 RT14 RT13 RT12 RT11 RT10...
Page 331: Software Interrupt Event Register 1 (Exti_Swier1)
RM0351 Extended interrupts and events controller (EXTI) Bits 22:18 FTx: Falling trigger event configuration bit of line x (x = 22 to 18) 0: Falling trigger disabled (for Event and Interrupt) for input line 1: Falling trigger enabled (for Event and Interrupt) for input line Bit 17 Reserved, must be kept at reset value.
Page 332: Pending Register 1 (Exti_Pr1)
Extended interrupts and events controller (EXTI) RM0351 12.5.6 Pending register 1 (EXTI_PR1) Address offset: 0x14 Reset value: undefined Res. Res. Res. Res. Res. Res. Res. Res. Res. PIF22 PIF21 PIF20 PIF19 PIF18 Res. PIF16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 PIF15 PIF14 PIF13...
Page 333: Event Mask Register 2 (Exti_Emr2)
RM0351 Extended interrupts and events controller (EXTI) 12.5.8 Event mask register 2 (EXTI_EMR2) Address offset: 0x24 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 334: Falling Trigger Selection Register 2 (Exti_Ftsr2)
Extended interrupts and events controller (EXTI) RM0351 12.5.10 Falling trigger selection register 2 (EXTI_FTSR2) Address offset: 0x2C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 335: Pending Register 2 (Exti_Pr2)
RM0351 Extended interrupts and events controller (EXTI) 12.5.12 Pending register 2 (EXTI_PR2) Address offset: 0x34 Reset value: undefined Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 336: Table 44. Extended Interrupt/Event Controller Register Map And Reset Values
Extended interrupts and events controller (EXTI) RM0351 12.5.13 EXTI register map Table 44 gives the EXTI register map and the reset values. Table 44. Extended interrupt/event controller register map and reset values Offset Register EXTI_IMR1 0x00 Reset value EXTI_EMR1 0x04 Reset value EXTI_RTSR1 0x08...
Page 337: Cyclic Redundancy Check Calculation Unit (Crc)
RM0351 Cyclic redundancy check calculation unit (CRC) Cyclic redundancy check calculation unit (CRC) 13.1 Introduction The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16- or 32-bit data word and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity.
Page 338: Figure 28. Crc Calculation Unit Block Diagram
Cyclic redundancy check calculation unit (CRC) RM0351 13.3 CRC functional description Figure 28. CRC calculation unit block diagram The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to input new data (write access), and holds the result of the previous CRC calculation (read access).
Page 339: Crc Registers
RM0351 Cyclic redundancy check calculation unit (CRC) The CRC calculator can be initialized to a programmable value using the RESET control bit in the CRC_CR register (the default value is 0xFFFFFFFF). The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR register is automatically initialized upon CRC_INIT register write access.
Page 340: Independent Data Register (Crc_Idr)
Cyclic redundancy check calculation unit (CRC) RM0351 13.4.2 Independent data register (CRC_IDR) Address offset: 0x04 Reset value: 0x0000 0000 IDR[31:16] IDR[15:0] 13.4.3 Control register (CRC_CR) Bits 31:0 IDR[31:0]: General-purpose 32-bit data register bits These bits can be used as a temporary storage location for one byte. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register Address offset: 0x08 Reset value: 0x0000 0000...
Page 341: Initial Crc Value (Crc_Init)
RM0351 Cyclic redundancy check calculation unit (CRC) Bits 4:3 POLYSIZE[1:0]: Polynomial size These bits control the size of the polynomial. 00: 32 bit polynomial 01: 16 bit polynomial 10: 8 bit polynomial 11: 7 bit polynomial Bits 2:1 Reserved, must be kept cleared. Bit 0 RESET: RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register.
Page 342: Table 45. Crc Register Map And Reset Values
Cyclic redundancy check calculation unit (CRC) RM0351 13.4.6 CRC register map Table 45. CRC register map and reset values Offset Register CRC_DR DR[31:0] 0x00 Reset value CRC_IDR IDR[31:0] 0x04 Reset value CRC_CR 0x08 Reset value CRC_INIT CRC_INIT[31:0] 0x10 Reset value CRC_POL Polynomial coefficients 0x14...
Page 343: Flexible Static Memory Controller (Fsmc)
RM0351 Flexible static memory controller (FSMC) Flexible static memory controller (FSMC) The Flexible static memory controller (FSMC) includes two memory controllers: • The NOR/PSRAM memory controller • The NAND memory controller This memory controller is also named Flexible memory controller (FMC). 14.1 FMC main features The FMC functional block makes the interface with: synchronous and asynchronous static...
Page 344: Figure 29. Fmc Block Diagram
Flexible static memory controller (FSMC) RM0351 The FMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up. However, the settings can be changed at any time. 14.2 Block diagram The FMC consists of the following main blocks:...
Page 345: Ahb Interface
RM0351 Flexible static memory controller (FSMC) 14.3 AHB interface The AHB slave interface allows internal CPUs and other bus master peripherals to access the external memories. AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses.
Page 346: External Device Address Mapping
Flexible static memory controller (FSMC) RM0351 transactions are allowed (the controller reads the entire 16-bit memory word and uses only the required byte). Wrap support for NOR Flash/PSRAM Wrap burst mode for synchronous memories is not supported. The memories must be configured in linear burst mode of undefined length.
Page 347: Table 46. Nor/Psram Bank Selection
RM0351 Flexible static memory controller (FSMC) Figure 30. FMC memory banks 14.4.1 NOR/PSRAM address mapping HADDR[27:26] bits are used to select one of the four memory banks as shown in Table Table 46. NOR/PSRAM bank selection HADDR[27:26] Selected bank Bank 1 - NOR/PSRAM 1 Bank 1 - NOR/PSRAM 2 Bank 1 - NOR/PSRAM 3 Bank 1 - NOR/PSRAM 4...
Page 348: Table 48. Nand Memory Mapping And Timing Registers
Flexible static memory controller (FSMC) RM0351 1. In case of a 16-bit external memory width, the FMC will internally use HADDR[25:1] to generate the address for external memory FMC_A[24:0]. Whatever the external memory width, FMC_A[0] should be connected to external memory address A[0]. 14.4.2 NAND Flash memory address mapping The NAND bank is divided into memory areas as indicated in...
Page 349: Nor Flash/Psram Controller
RM0351 Flexible static memory controller (FSMC) 14.5 NOR Flash/PSRAM controller The FMC generates the appropriate signal timings to drive the following types of memories: • Asynchronous SRAM and ROM – 8 bits – 16 bits • PSRAM (Cellular RAM) – Asynchronous mode –...
Page 350: Table 50. Programmable Nor/Psram Access Parameters
Flexible static memory controller (FSMC) RM0351 Table 50. Programmable NOR/PSRAM access parameters Parameter Function Access mode Unit Min. Max. Address Duration of the address AHB clock cycle Asynchronous setup setup phase (HCLK) Duration of the address hold Asynchronous, AHB clock cycle Address hold phase muxed I/Os...
Page 351: Table 52. 16-Bit Multiplexed I/O Nor Flash Memory
RM0351 Flexible static memory controller (FSMC) NOR Flash memory, 16-bit multiplexed I/Os Table 52. 16-bit multiplexed I/O NOR Flash memory FMC signal name Function Clock (for synchronous access) A[25:16] Address bus 16-bit multiplexed, bidirectional address/data bus (the 16-bit address AD[15:0] A[15:0] and data D[15:0] are multiplexed on the databus) NE[x] Chip Select, x = 1..4...
Page 352: Table 55. Nor Flash/Psram: Example Of Supported Memories And Transactions
Flexible static memory controller (FSMC) RM0351 Table 54. 16-Bit multiplexed I/O PSRAM (continued) FMC signal name I/O Function NE[x] Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM)) Output enable Write enable NL(= NADV) Address valid PSRAM input (memory signal name: NADV) NWAIT PSRAM wait input signal to the FMC NBL[1:0]...
Page 353: General Timing Rules
RM0351 Flexible static memory controller (FSMC) Table 55. NOR Flash/PSRAM: example of supported memories and transactions Allowed/ Memory Device Mode data Comments data size size allowed Asynchronous Asynchronous Use of byte lanes NBL[1:0] Asynchronous Asynchronous Asynchronous Split into 2 FMC accesses PSRAM Asynchronous Split into 2 FMC accesses...
Page 354: Figure 31. Mode1 Read Access Waveforms
Flexible static memory controller (FSMC) RM0351 14.5.4 NOR Flash/PSRAM controller asynchronous transactions Asynchronous static memories (NOR Flash, PSRAM, SRAM) • Signals are synchronized by the internal clock HCLK. This clock is not issued to the memory • The FMC always samples the data before de-asserting the NOE signal. This guarantees that the memory data hold timing constraint is met (minimum Chip Enable high to data transition is usually 0 ns) •...
Page 355: Table 56. Fmc_Bcrx Bit Fields
RM0351 Flexible static memory controller (FSMC) Figure 32. Mode1 write access waveforms The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the DATAST value must be greater than zero (DATAST >...
Page 356: Table 57. Fmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0351 Table 56. FMC_BCRx bit fields (continued) Bit number Bit name Value to set MTYP As needed, exclude 0x2 (NOR Flash memory) MUXE MBKEN Table 57. FMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29-28...
Page 357: Figure 33. Modea Read Access Waveforms
RM0351 Flexible static memory controller (FSMC) Mode A - SRAM/PSRAM (CRAM) OE toggling Figure 33. ModeA read access waveforms 1. NBL[1:0] are driven low during the read access Figure 34. ModeA write access waveforms DocID024597 Rev 3 357/1693...
Page 358: Table 58. Fmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0351 The differences compared with Mode1 are the toggling of NOE and the independent read and write timings. Table 58. FMC_BCRx bit fields Bit number Bit name Value to set 31-21 Reserved 0x000 CCLKEN As needed CBURSTRW 0x0 (no effect in asynchronous mode) 18:16...
Page 359: Table 60. Fmc_Bwtrx Bit Fields
RM0351 Flexible static memory controller (FSMC) Table 60. FMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST HCLK cycles) for write 15-8 DATAST...
Page 360: Figure 36. Mode2 Write Access Waveforms
Flexible static memory controller (FSMC) RM0351 Figure 36. Mode2 write access waveforms Figure 37. ModeB write access waveforms The differences with Mode1 are the toggling of NWE and the independent read and write timings when extended mode is set (Mode B). 360/1693 DocID024597 Rev 3...
Page 361: Table 61. Fmc_Bcrx Bit Fields
RM0351 Flexible static memory controller (FSMC) Table 61. FMC_BCRx bit fields Bit number Bit name Value to set 31-21 Reserved 0x000 CCLKEN As needed CBURSTRW 0x0 (no effect in asynchronous mode) 18:16 CPSIZE 0x0 (no effect in asynchronous mode) ASYNCWAIT Set to 1 if the memory supports this feature.
Page 362: Table 63. Fmc_Bwtrx Bit Fields
Flexible static memory controller (FSMC) RM0351 Table 63. FMC_BWTRx bit fields Bit number Bit name Value to set 31-30 Reserved 29-28 ACCMOD 0x1 if extended mode is set 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK) Duration of the access second phase (DATAST HCLK cycles) for 15-8 DATAST...
Page 363: Table 64. Fmc_Bcrx Bit Fields
RM0351 Flexible static memory controller (FSMC) Figure 39. ModeC write access waveforms The differences compared with Mode1 are the toggling of NOE and the independent read and write timings. Table 64. FMC_BCRx bit fields Bit number Bit name Value to set 31-21 Reserved 0x000...
Page 364: Table 65. Fmc_Btrx Bit Fields
Flexible static memory controller (FSMC) RM0351 Table 64. FMC_BCRx bit fields (continued) Bit number Bit name Value to set MUXEN MBKEN Table 65. FMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT 23-20 CLKDIV 19-16 BUSTURN...
Page 365: Figure 40. Moded Read Access Waveforms
RM0351 Flexible static memory controller (FSMC) Mode D - asynchronous access with extended address Figure 40. ModeD read access waveforms Figure 41. ModeD write access waveforms DocID024597 Rev 3 365/1693...
Page 366: Table 67. Fmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0351 The differences with Mode1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings. Table 67. FMC_BCRx bit fields Bit number Bit name Value to set 31-21 Reserved 0x000...
Page 367: Table 69. Fmc_Bwtrx Bit Fields
RM0351 Flexible static memory controller (FSMC) Table 69. FMC_BWTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care 19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK) Duration of the second access phase (DATAST + 1 HCLK cycles) for 15-8 DATAST...
Page 368: Table 70. Fmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0351 Figure 43. Muxed write access waveforms The difference with ModeD is the drive of the lower address byte(s) on the data bus. Table 70. FMC_BCRx bit fields Bit number Bit name Value to set 31-21 Reserved 0x000...
Page 369: Table 71. Fmc_Btrx Bit Fields
RM0351 Flexible static memory controller (FSMC) Table 70. FMC_BCRx bit fields (continued) Bit number Bit name Value to set MUXEN MBKEN Table 71. FMC_BTRx bit fields Bit number Bit name Value to set 31:30 Reserved 29-28 ACCMOD 27-24 DATLAT Don’t care 23-20 CLKDIV Don’t care...
Page 370: Figure 44. Asynchronous Wait During A Read Access Waveforms
Flexible static memory controller (FSMC) RM0351 The memory asserts the WAIT signal aligned to NOE/NWE which toggles: DATAST ≥ × HCLK max_wait_assertion_time The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling): > max_wait_assertion_time address_phase hold_phase then: ≥...
Page 371: Figure 45. Asynchronous Wait During A Write Access Waveforms
RM0351 Flexible static memory controller (FSMC) Figure 45. Asynchronous wait during a write access waveforms 1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register. 14.5.5 Synchronous transactions The memory clock, FMC_CLK, is a submultiple of HCLK. It depends on the value of CLKDIV and the MWID/ AHB data size, following the formula given below: FMC_CLK divider ratio max CLKDIV...
Page 372 Flexible static memory controller (FSMC) RM0351 Caution: Some NOR Flash memories include the NADV Low cycle in the data latency count, so that the exact relation between the NOR Flash latency and the FMC DATLAT parameter can be either: • NOR Flash latency = (DATLAT + 2) CLK clock cycles •...
Page 373: Figure 46. Wait Configuration Waveforms
RM0351 Flexible static memory controller (FSMC) Figure 46. Wait configuration waveforms DocID024597 Rev 3 373/1693...
Page 374: Table 72. Fmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0351 Figure 47. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) 1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low. Table 72.
Page 375: Table 73. Fmc_Btrx Bit Fields
RM0351 Flexible static memory controller (FSMC) Table 72. FMC_BCRx bit fields (continued) Bit number Bit name Value to set BURSTEN Reserved FACCEN Set according to memory support (NOR Flash memory) MWID As needed MTYP 0x1 or 0x2 MUXEN As needed MBKEN Table 73.
Page 376: Table 74. Fmc_Bcrx Bit Fields
Flexible static memory controller (FSMC) RM0351 Figure 48. Synchronous multiplexed write mode waveforms - PSRAM (CRAM) 1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0. 2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active. Table 74.
Page 377: Table 75. Fmc_Btrx Bit Fields
RM0351 Flexible static memory controller (FSMC) Table 74. FMC_BCRx bit fields (continued) Bit number Bit name Value to set WAITCFG Reserved WAITPOL to be set according to memory BURSTEN no effect on synchronous write Reserved FACCEN Set according to memory support MWID As needed MTYP...
Page 378: Nor/Psram Controller Registers
Flexible static memory controller (FSMC) RM0351 14.5.6 NOR/PSRAM controller registers SRAM/NOR-Flash chip-select control registers 1..4 (FMC_BCR1..4) Address offset: 8 * (x – 1), x = 1...4 Reset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4 This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.
Page 379 RM0351 Flexible static memory controller (FSMC) Bits 18:16 CPSIZE[2:0]: CRAM page size. These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size).
Page 380 Flexible static memory controller (FSMC) RM0351 Bit 8 BURSTEN: Burst enable bit. This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in burst mode: 0: Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode. 1: Burst mode enable.
Page 381 RM0351 Flexible static memory controller (FSMC) Res. Res. ACCMOD DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET Bits 31:30 Reserved, must be kept at reset value Bits 29:28 ACCMOD[1:0]: Access mode Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
Page 382 Flexible static memory controller (FSMC) RM0351 Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read (and read-to- write) transaction. The programmed bus turnaround delay is inserted between an asynchronous read (muxed or mode D) or write transaction and any other asynchronous /synchronous read or write to or from a static bank.
Page 383 RM0351 Flexible static memory controller (FSMC) Bits 7:4 ADDHLD[3:0]: Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure 31 Figure 43), used in mode D or multiplexed accesses: 0000: Reserved 0001: ADDHLD phase duration =1 ×...
Page 384 Flexible static memory controller (FSMC) RM0351 Bits 29:28 ACCMOD[1:0]: Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1. 00: access mode A 01: access mode B 10: access mode C 11: access mode D...
Page 385: Nand Flash Controller
RM0351 Flexible static memory controller (FSMC) Bits 3:0 ADDSET[3:0]: Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 31 Figure 43), used in asynchronous accesses: 0000: ADDSET phase duration = 0 ×...
Page 386: Table 76. Programmable Nand Flash Access Parameters
Flexible static memory controller (FSMC) RM0351 Table 76. Programmable NAND Flash access parameters Parameter Function Access mode Unit Min. Max. Number of clock cycles (HCLK) Memory setup AHB clock cycle required to set up the address Read/Write time (HCLK) before the command assertion Minimum duration (in HCLK clock AHB clock cycle Memory wait...
Page 387: Table 78. 16-Bit Nand Flash
RM0351 Flexible static memory controller (FSMC) 16-bit NAND Flash memory Table 78. 16-bit NAND Flash FMC signal name Function A[17] NAND Flash address latch enable (ALE) signal A[16] NAND Flash command latch enable (CLE) signal D[15:0] 16-bit multiplexed, bidirectional address/data bus Chip Select NOE(= NRE) Output enable (memory signal name: read enable, NRE)
Page 388: Table 79. Supported Memories And Transactions
Flexible static memory controller (FSMC) RM0351 14.6.2 NAND Flash supported memories and transactions Table 79 shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the NAND Flash controller are shown in gray. Table 79. Supported memories and transactions Memory Allowed/ Device...
Page 389: Figure 49. Nand Flash Controller Waveforms For Common Memory Access
RM0351 Flexible static memory controller (FSMC) Figure 49. NAND Flash controller waveforms for common memory access 1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses. 14.6.4 NAND Flash operations The command latch enable (CLE) and address latch enable (ALE) signals of the NAND Flash memory device are driven by address signals from the FMC controller.
Page 390: Figure 50. Access To Non 'Ce Don't Care' Nand-Flash
Flexible static memory controller (FSMC) RM0351 details in Section 14.6.5: NAND Flash prewait functionality). The controller waits for the NAND Flash memory to be ready (R/NB signal high), before starting a new access to the same or another memory bank. While waiting, the controller holds the NCE signal active (low).
Page 391: In Nand Flash Memory
RM0351 Flexible static memory controller (FSMC) When this functionality is required, it can be ensured by programming the MEMHOLD value to meet the t timing. However any CPU read or write access to the NAND Flash memory has a hold delay of (MEMHOLD + 1) HCLK cycles inserted between the rising edge of the NWE signal and the next access.
Page 392: Nand Flashcontroller Registers
Flexible static memory controller (FSMC) RM0351 To perform an ECC computation: Enable the ECCEN bit in the FMC_PCR register. Write data to the NAND Flash memory page. While the NAND page is written, the ECC block computes the ECC value. Read the ECC value available in the FMC_ECCR register and store it in a variable.
Page 393 RM0351 Flexible static memory controller (FSMC) Bits 12:9 TCLR[3:0]: CLE to RE delay. Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period 0000: 1 HCLK cycle (default) 1111: 16 HCLK cycles Note: SET is MEMSET or ATTSET according to the addressed space.
Page 394 Flexible static memory controller (FSMC) RM0351 Res. Res. Res. Res. Res. Res. Res. Res. Res. FEMPT IFEN ILEN IREN Bits 31:7 Reserved, must be kept at reset value Bit 6 FEMPT: FIFO empty. Read-only bit that provides the status of the FIFO 0: FIFO not empty 1: FIFO empty Bit 5 IFEN: Interrupt falling edge detection enable bit...
Page 395 RM0351 Flexible static memory controller (FSMC) Bits 31:24 MEMHIZ[7:0]: Common memory x data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space on socket. This is only valid for write transactions: 0000 0000: 1 HCLK cycle 1111 1110: 255 HCLK cycles...
Page 396 Flexible static memory controller (FSMC) RM0351 Bits 31:24 ATTHIZ[7:0]: Attribute memory data bus Hi-Z time Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction: 0000 0000: 0 HCLK cycle 1111 1110: 255 HCLK cycles...
Page 397: Table 80. Ecc Result Relevant Bits
RM0351 Flexible static memory controller (FSMC) ECC result registers (FMC_ECCR) Address offset: 0x94 Reset value: 0x0000 0000 This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads the data from a NAND Flash memory page at the correct address (refer to Section 14.6.6: Computation of the error correction code (ECC) in NAND Flash...
Page 398: Table 81. Fmc Register Map
Flexible static memory controller (FSMC) RM0351 14.7 FMC register map The following table summarizes the FMC registers. Table 81. FMC register map Offset Register CPSIZE MWID MTYP FMC_BCR1 [2:0] [1:0] [1:0] 0x00 Reset value CPSIZE MWID MTYP FMC_BCR2 [2:0] [1:0] [1:0] 0x08 Reset value...
Page 399 RM0351 Flexible static memory controller (FSMC) Table 81. FMC register map (continued) Offset Register FMC_BWTR2 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x10C Reset value FMC_BWTR3 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] 0x114 Reset value ACCM FMC_BWTR4 BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0] OD[1:0] 0x11C Reset value ECCPS PWID FMC_PCR...
Page 400: Figure 51. Quadspi Block Diagram
Quad-SPI interface (QUADSPI) RM0351 Quad-SPI interface (QUADSPI) 15.1 Introduction The QUADSPI is a specialized communication interface targeting single, dual or quad SPI Flash memories. It can operate in any of the three following modes: • indirect mode: all the operations are performed using the QUADSPI registers •...
Page 401: Figure 52. An Example Of A Read Command In Quad Mode
RM0351 Quad-SPI interface (QUADSPI) The QUADSPI uses 6 signals to interface with a Flash memory: – CLK - Clock output – BK1_IO0/SO - Bidirectional IO in dual/quad modes or serial output in single mode – BK1_IO1/SI - Bidirectional IO in dual/quad modes or serial input in single mode –...
Page 402 Quad-SPI interface (QUADSPI) RM0351 The address phase can send 1 bit at a time (over SO in single SPI mode), 2 bits at a time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI mode).
Page 403: Quadspi Signal Interface Protocol Modes
RM0351 Quad-SPI interface (QUADSPI) In indirect write mode the data to be sent to the Flash memory must be written to the QUADSPI_DR register, while in indirect read mode the data received from the Flash memory is obtained by reading from the QUADSPI_DR register. In memory-mapped mode, the data which is read is sent back directly over the AHB to the Cortex or to a DMA.
Page 404: Figure 53. An Example Of A Ddr Command In Quad Mode
Quad-SPI interface (QUADSPI) RM0351 In each phase which is configured in quad mode, IO0/IO1/IO2/IO3 are all are at high- impedance (input) during the data phase for read operations, and outputs in all other cases. In the dummy phase when DMODE = 11, IO0/IO1/IO2/IO3 are all high-impedance. IO2 and IO3 are used only in Quad SPI mode.
Page 405 RM0351 Quad-SPI interface (QUADSPI) When FMODE = 00 (QUADSPI_CCR[27:26]), the QUADSPI is in indirect write mode, where bytes are sent to the Flash memory during the data phase. Data are provided by writing to the data register (QUADSPI_DR). When FMODE = 01, the QUADSPI is in indirect read mode, where bytes are received from the Flash memory during the data phase.
Page 406: Quadspi Status Flag Polling Mode
Quad-SPI interface (QUADSPI) RM0351 Byte/halfword accesses to QUADSPI_DR must be done only to the least significant byte/halfword of the 32-bit register. FTHRES[3:0] is used to define a FIFO threshold. When the threshold is reached, the FTF (FIFO threshold flag) is set. In indirect read mode, FTF is set when the number of valid bytes to be read from the FIFO is above the threshold.
Page 407: Quadspi Memory-Mapped Mode
RM0351 Quad-SPI interface (QUADSPI) 15.3.6 QUADSPI memory-mapped mode When configured in memory-mapped mode, the external SPI device is seen as an internal memory. It is forbidden to access QUADSPI Flash bank area before having properly configured and enabled the QUADSPI peripheral. No more than 256MB can addressed even if the Flash memory capacity is larger.
Page 408: Quadspi Delayed Data Sampling
Quad-SPI interface (QUADSPI) RM0351 15.3.8 QUADSPI delayed data sampling By default, the QUADSPI samples the data driven by the Flash memory one half of a CLK cycle after the Flash memory drives the signal. In case of external signal delays, it may be beneficial to sample the data later. Using the SSHIFT bit (QUADSPI_CR[4]), the sampling of the data can be shifted by half of a CLK cycle.
Page 409 RM0351 Quad-SPI interface (QUADSPI) Specify a number of data bytes to read or write in the QUADSPI_DLR Specify the frame format, mode and instruction code in the QUADSPI_CCR Specify optional alternate byte to be sent right after the address phase in the QUADSPI_ABR Specify the operating mode in the QUADSPI_CR.
Page 410: Sending The Instruction Only Once
Quad-SPI interface (QUADSPI) RM0351 The maximum amount of data read in each frame is 4 bytes. If more data is requested in QUADSPI_DLR, it will be ignored and only 4 bytes will be read. The periodicity is specified in the QUADSPI_PISR register. Once the status data has been retrieved, it can internally be processed i order to: •...
Page 411: Figure 54. Ncs When Ckmode = 0 (T = Clk Period)
RM0351 Quad-SPI interface (QUADSPI) FSIZE[4:0] in the QUADSPI_DCR): this will set the TEF and an interrupt is generated if enabled. • Also in indirect mode, if the address plus the data length exceeds the Flash memory size, TEF will be set as soon as the access is triggered. •...
Page 412: Figure 55. Ncs When Ckmode = 1 In Sdr Mode (T = Clk Period)
Quad-SPI interface (QUADSPI) RM0351 Figure 55. nCS when CKMODE = 1 in SDR mode (T = CLK period) When CKMODE = 1 (“mode3”) and DDRM = 1 (DDR mode), nCS falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation final active rising CLK edge, as shown in Figure 56.
Page 413: Table 82. Quadspi Interrupt Requests
RM0351 Quad-SPI interface (QUADSPI) 15.4 QUADSPI interrupts An interrupt can be produced on the following events: • Timeout • Status match • FIFO threshold • Transfer complete • Transfer error Separate interrupt enable bits are available for flexibility. Table 82. QUADSPI interrupt requests Interrupt event Event flag Enable control bit...
Page 414: Quadspi Registers
Quad-SPI interface (QUADSPI) RM0351 15.5 QUADSPI registers 15.5.1 QUADSPI control register (QUADSPI_CR) Address offset: 0x0000 Reset value: 0x0000 0000 PRESCALER APMS Res. TOIE SMIE FTIE TCIE TEIE Res. Res. Res. Res. FTHRES Res. Res. Res. SSHIFT TCEN DMAEN ABORT Bits 31: 24 PRESCALER[7:0]: Clock prescaler This field defines the scaler factor for generating CLK based on the AHB clock (value+1).
Page 415 RM0351 Quad-SPI interface (QUADSPI) Bit 18 FTIE: FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 17 TCIE: Transfer complete interrupt enable This bit enables the transfer complete interrupt. 0: Interrupt disabled 1: Interrupt enabled Bit 16 TEIE: Transfer error interrupt enable This bit enables the transfer error interrupt.
Page 416: Quadspi Device Configuration Register (Quadspi_Dcr)
Quad-SPI interface (QUADSPI) RM0351 Bit 3 TCEN: Timeout counter enable This bit is valid only when memory-mapped mode (FMODE = 11) is selected. Activating this bit causes the chip select (nCS) to be released (and thus reduces consumption) if there has not been an access after a certain amount of time, where this time is defined by TIMEOUT[15:0] (QUADSPI_LPTR).
Page 417: Quadspi Status Register (Quadspi_Sr)
RM0351 Quad-SPI interface (QUADSPI) Bits 31: 21 Reserved, must be kept at reset value. Bits 20: 16 FSIZE[4:0]: Flash memory size This field defines the size of external memory using the following formula: [FSIZE+1] Number of bytes in Flash memory = 2 FSIZE+1 is effectively the number of address bits required to address the Flash memory.
Page 418: Quadspi Flag Clear Register (Quadspi_Fcr)
Quad-SPI interface (QUADSPI) RM0351 Bit 5 BUSY: Busy This bit is set when an operation is on going. This bit clears automatically when the operation with the Flash memory is finished and the FIFO is empty. Bit 4 TOF: Timeout flag This bit is set when timeout occurs.
Page 419: Quadspi Data Length Register (Quadspi_Dlr)
RM0351 Quad-SPI interface (QUADSPI) 15.5.5 QUADSPI data length register (QUADSPI_DLR) Address offset: 0x0010 Reset value: 0x0000 0000 DL[31:16] DL[15:0] Bits 31:0 DL[31: 0]: Data length Number of data to be retrieved (value+1) in indirect and status-polling modes. A value no greater than 3 (indicating 4 bytes) should be used for status-polling mode. All 1s in indirect mode means undefined length, where QUADSPI will continue until the end of memory, as defined by FSIZE.
Page 420 Quad-SPI interface (QUADSPI) RM0351 Bit 31 DDRM: Double data rate mode This bit sets the DDR mode for the address, alternate byte and data phase: 0: DDR Mode disabled 1: DDR Mode enabled This field can be written only when BUSY = 0. Bits 30:29 Reserved, must be kept at reset value.
Page 421: Quadspi Address Register (Quadspi_Ar)
RM0351 Quad-SPI interface (QUADSPI) Bits 13:12 ADSIZE[1:0]: Address size This bit defines address size: 00: 8-bit address 01: 16-bit address 10: 24-bit address 11: 32-bit address This field can be written only when BUSY = 0. Bits 11:10 ADMODE[1:0]: Address mode This field defines the address phase mode of operation: 00: No address 01: Address on a single line...
Page 422: Quadspi Data Register (Quadspi_Dr)
Quad-SPI interface (QUADSPI) RM0351 ALTERNATE[31:16] ALTERNATE[15:0] Bits 31: 0 ALTERNATE[31: 0]: Alternate Bytes Optional data to be send to the external SPI device right after the address. This field can be written only when BUSY = 0. 15.5.9 QUADSPI data register (QUADSPI_DR) Address offset: 0x0020 Reset value: 0x0000 0000 DATA[31:16]...
Page 423: Quadspi Polling Status Match Register (Quadspi _Psmar)
RM0351 Quad-SPI interface (QUADSPI) MASK[31:16] MASK[15:0] Bits 31: 0 MASK[31: 0]: Status mask Mask to be applied to the status bytes received in polling mode. For bit n: 0: Bit n of the data received in automatic polling mode is masked and its value is not considered in the matching logic 1: Bit n of the data received in automatic polling mode is unmasked and its value is considered in the matching logic...
Page 424: Quadspi Low-Power Timeout Register (Quadspi_Lptr)
Quad-SPI interface (QUADSPI) RM0351 Bits 31: 16 Reserved, must be kept at reset value. Bits 15: 0 INTERVAL[15: 0]: Polling interval Number of CLK cycles between to read during automatic polling phases. This field can be written only when BUSY = 0. 15.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR) Address offset: 0x0030...
Page 425: Table 83. Quadspi Register Map And Reset Values
RM0351 Quad-SPI interface (QUADSPI) 15.5.14 QUADSPI register map Table 83. QUADSPI register map and reset values Offset Register FTHRES QUADSPI_CR PRESCALER[7:0] [3:0] 0x0000 Reset value QUADSPI_DCR FSIZE[4:0] CSHT 0x0004 Reset value QUADSPI_SR FLEVEL[5:0] 0x0008 Reset value QUADSPI_FCR 0x000C Reset value QUADSPI_DLR DL[31:0] 0x0010...
Page 426: Introduction
Analog-to-digital converters (ADC) RM0351 Analog-to-digital converters (ADC) 16.1 Introduction This section describes the implementation of up to 3 ADCs • ADC1 and ADC2 are tightly coupled and can operate in dual mode (ADC1 is master). • ADC3 is controlled independently. Each ADC consists of a 12-bit successive approximation analog-to-digital converter.
Page 427: Adc Main Features
RM0351 Analog-to-digital converters (ADC) 16.2 ADC main features • High-performance features – Up to 3x ADCs, out of which two of them can operate in dual mode – ADC1 is connected to 16 external channels + 3 internal channels – ADC2 is connected to 16 external channels + 2 internal channels –...
Page 428 Analog-to-digital converters (ADC) RM0351 • Start-of-conversion can be initiated: – by software for both regular and injected conversions – by hardware triggers with configurable polarity (internal timers events or GPIO input events) for both regular and injected conversions • Conversion modes –...
Page 429: Figure 58. Adc Block Diagram
RM0351 Analog-to-digital converters (ADC) 16.3 ADC functional description 16.3.1 ADC block diagram Figure 58 shows the ADC block diagram and Table 85 gives the ADC pin description. Figure 58. ADC block diagram DocID024597 Rev 3 429/1693...
Page 430: Table 84. Adc Internal Signals
Analog-to-digital converters (ADC) RM0351 16.3.2 Pins and internal signals Table 84. ADC internal signals Signal Internal signal name Description type Up to 16 external trigger inputs for the regular conversions (can be connected to on-chip timers). EXT[15:0] Inputs These inputs are shared between the ADC master and the ADC slave.
Page 431: Clocks
RM0351 Analog-to-digital converters (ADC) 16.3.3 Clocks Dual clock domain architecture The dual clock-domain architecture means that the ADCs clock is independent from the AHB bus clock. The input clock is the same for the three ADCs and can be selected between two different clock sources (see Figure 59: ADC clock scheme):...
Page 432: Figure 59. Adc Clock Scheme
Analog-to-digital converters (ADC) RM0351 Figure 59. ADC clock scheme Clock ratio constraint between ADC clock and AHB clock There are generally no constraints to be respected for the ratio between the ADC clock and the AHB clock except if some injected channels are programmed. In this case, it is mandatory to respect the following ratio: •...
Page 433: Figure 60. Adc1 Connectivity
RM0351 Analog-to-digital converters (ADC) 16.3.4 ADC1/2/3 connectivity ADC1, ADC2 and ADC3 are tightly coupled and share some external channels as described in the below figures. Figure 60. ADC1 connectivity DocID024597 Rev 3 433/1693...
Page 434: Figure 61. Adc2 Connectivity
Analog-to-digital converters (ADC) RM0351 Figure 61. ADC2 connectivity 434/1693 DocID024597 Rev 3...
Page 435: Figure 62. Adc3 Connectivity
RM0351 Analog-to-digital converters (ADC) Figure 62. ADC3 connectivity DocID024597 Rev 3 435/1693...
Page 436: Slave Ahb Interface
Analog-to-digital converters (ADC) RM0351 16.3.5 Slave AHB interface The ADCs implement an AHB slave port for control/status register and data access. The features of the AHB interface are listed below: • Word (32-bit) accesses • Single cycle response • Response to all read/write accesses to the registers with zero wait states. The AHB slave interface does not support split/retry requests, and never generates AHB errors.
Page 437: Calibration (Adcal, Adcaldif, Adcx_Calfact)
RM0351 Analog-to-digital converters (ADC) In differential input mode, the analog voltage to be converted for channel “i” is the difference between the external voltage ADC_INi (positive input) and ADC_INi+1 (negative input). When ADC is configured as differential mode, both input should be biased at (VREF+) / 2 voltage.
Page 438: Figure 63. Adc Calibration
Analog-to-digital converters (ADC) RM0351 ADCx_CALFACT register without recalibrating, supposing that the software has previously saved the calibration factor delivered during the previous calibration. The calibration factor can be written if the ADC is enabled but not converting (ADEN=1 and ADSTART=0 and JADSTART=0). Then, at the next start of conversion, the calibration factor will automatically be injected into the analog ADC.
Page 439: Figure 64. Updating The Adc Calibration Factor
RM0351 Analog-to-digital converters (ADC) Figure 64. Updating the ADC calibration factor Converting single-ended and differential analog inputs with a single ADC If the ADC is supposed to convert both differential and single-ended inputs, two calibrations must be performed, one with ADCALDIF=0 and one with ADCALDIF=1. The procedure is the following: Disable the ADC.
Page 440: Adc On-Off Control (Aden, Addis, Adrdy)
Analog-to-digital converters (ADC) RM0351 16.3.9 ADC on-off control (ADEN, ADDIS, ADRDY) First of all, follow the procedure explained in Section 16.3.6: ADC Deep-Power-Down Mode (DEEPPWD) & ADC Voltage Regulator (ADVREGEN)). Once DEEPPWD=0 and ADVREGRN=1, the ADC can be enabled and the ADC needs a stabilization time of t before it starts converting accurately, as shown in Figure...
Page 441: Figure 66. Enabling / Disabling The Adc
RM0351 Analog-to-digital converters (ADC) Figure 66. Enabling / Disabling the ADC 16.3.10 Constraints when writing the ADC control bits The software is allowed to write the RCC control bits to configure and enable the ADC clock (refer to RCC Section), the control bits DIFSEL in the ADCx_DIFSEL register and the control bits ADCAL and ADEN in the ADCx_CR register, only if the ADC is disabled (ADEN must be equal to 0).
Page 442: Channel Selection (Sqrx, Jsqrx)
Analog-to-digital converters (ADC) RM0351 16.3.11 Channel selection (SQRx, JSQRx) There are up to 19 multiplexed channels per ADC: • 5 fast analog inputs coming from GPIO pads (ADC_IN1..5) • Up to 10 slow analog inputs coming from GPIO pads (ADC_IN6..15). Depending on the products, not all of them are available on GPIO pads.
Page 443: Single Conversion Mode (Cont=0)
RM0351 Analog-to-digital converters (ADC) Each channel can be sampled with a different sampling time which is programmable using the SMP[2:0] bits in the ADCx_SMPR1 and ADCx_SMPR2 registers. It is therefore possible to select among the following sampling time values: • SMP = 000: 2.5 ADC clock cycles •...
Page 444: Continuous Conversion Mode (Cont=1)
Analog-to-digital converters (ADC) RM0351 Inside the injected sequence, after each conversion is complete: • The converted data are stored into one of the four 16-bit ADCx_JDRy registers • The JEOC (end of injected conversion) flag is set • An interrupt is generated if the JEOCIE bit is set After the regular sequence is complete: •...
Page 445: Starting Conversions (Adstart, Jadstart)
RM0351 Analog-to-digital converters (ADC) 16.3.15 Starting conversions (ADSTART, JADSTART) Software starts ADC regular conversions by setting ADSTART=1. When ADSTART is set, the conversion starts: • Immediately: if EXTEN = 0x0 (software trigger) • At the next active edge of the selected regular hardware trigger: if EXTEN /= 0x0 Software starts ADC injected conversions by setting JADSTART=1.
Page 446: Figure 67. Analog To Digital Conversion Time
Analog-to-digital converters (ADC) RM0351 Figure 67. Analog to digital conversion time 1. T depends on SMP[2:0] SMPL 2. T depends on RES[2:0] 16.3.17 Stopping an ongoing conversion (ADSTP, JADSTP) The software can decide to stop regular conversions ongoing by setting ADSTP=1 and injected conversions ongoing by setting JADSTP=1.
Page 447: Figure 68. Stopping Ongoing Regular Conversions
RM0351 Analog-to-digital converters (ADC) Figure 68. Stopping ongoing regular conversions Figure 69. Stopping ongoing regular and injected conversions DocID024597 Rev 3 447/1693...
Page 448: Table 86. Configuring The Trigger Polarity For Regular External Triggers
Analog-to-digital converters (ADC) RM0351 16.3.18 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) A conversion or a sequence of conversions can be triggered either by software or by an external event (e.g. timer capture, input pins). If the EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, then external events are able to trigger a conversion with the selected polarity.
Page 449: Table 88. Adc1, Adc2 And Adc3 - External Triggers For Regular Channels
RM0351 Analog-to-digital converters (ADC) Note: The regular trigger selection cannot be changed on-the-fly. The injected trigger selection can be anticipated and changed on-the-fly. Refer to Section 16.3.21: Queue of context for injected conversions on page 453 Each ADC master shares the same input triggers with its ADC slave as described in Figure Figure 70.
Page 450: Table 89. Adc1, Adc2 And Adc3 - External Trigger For Injected Channels
Analog-to-digital converters (ADC) RM0351 Table 88. ADC1, ADC2 and ADC3 - External triggers for regular channels (continued) Name Source Type EXTSEL[3:0] EXT10 TIM1_TRGO2 event Internal signal from on-chip timers 1010 EXT11 TIM2_TRGO event Internal signal from on-chip timers 1011 EXT12 TIM4_TRGO event Internal signal from on-chip timers 1100...
Page 451 RM0351 Analog-to-digital converters (ADC) reset and the injected channel sequence switches are launched (all the injected channels are converted once). Then, the regular conversion of the regular group of channels is resumed from the last interrupted regular conversion. If a regular event occurs during an injected conversion, the injected conversion is not interrupted but the regular sequence is executed at the end of the injected sequence.
Page 452: Figure 71. Injected Conversion Latency
Analog-to-digital converters (ADC) RM0351 Figure 71. Injected conversion latency 1. The maximum latency value can be found in the electrical characteristics of the STM32L4x6 datasheet. 16.3.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) Regular group mode This mode is enabled by setting the DISCEN bit in the ADCx_CFGR register.
Page 453: Queue Of Context For Injected Conversions
RM0351 Analog-to-digital converters (ADC) Note: When a regular group is converted in discontinuous mode, no rollover occurs (the last subgroup of the sequence can have less than n conversions). When all subgroups are converted, the next trigger starts the conversion of the first subgroup.
Page 454 Analog-to-digital converters (ADC) RM0351 All the parameters of the context are defined into a single register ADCx_JSQR and this register implements a queue of 2 buffers, allowing the bufferization of up to 2 sets of parameters: • The JSQR register can be written at any moment even when injected conversions are ongoing.
Page 455: Figure 72. Example Of Jsqr Queue Of Context (Sequence Change)
RM0351 Analog-to-digital converters (ADC) Behavior when changing the trigger or sequence context Figure 72 Figure 73 show the behavior of the context Queue when changing the sequence or the triggers. Figure 72. Example of JSQR queue of context (sequence change) 1.
Page 456: Figure 74. Example Of Jsqr Queue Of Context With Overflow Before Conversion
Analog-to-digital converters (ADC) RM0351 Queue of context: Behavior when a queue overflow occurs Figure 74 Figure 75 show the behavior of the context Queue if an overflow occurs before or during a conversion. Figure 74. Example of JSQR queue of context with overflow before conversion 1.
Page 457: Figure 76. Example Of Jsqr Queue Of Context With Empty Queue (Case Jqm=0)
RM0351 Analog-to-digital converters (ADC) It is recommended to manage the queue overflows as described below: • After each P context write into JSQR register, flag JQOVF shows if the write has been ignored or not (an interrupt can be generated). •...
Page 458: Figure 78. Flushing Jsqr Queue Of Context By Setting Jadstp=1 (Jqm=0). Case When Jadstp Occurs During An Ongoing Conversion
Analog-to-digital converters (ADC) RM0351 Flushing the queue of context The figures below show the behavior of the context Queue in various situations when the queue is flushed. Figure 78. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion. 1.
Page 459: Figure 80. Flushing Jsqr Queue Of Context By Setting Jadstp=1 (Jqm=0). Case When Jadstp Occurs Outside An Ongoing Conversion
RM0351 Analog-to-digital converters (ADC) Figure 80. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs outside an ongoing conversion 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Figure 81.
Page 460: Figure 82. Flushing Jsqr Queue Of Context By Setting Addis=1 (Jqm=0)
Analog-to-digital converters (ADC) RM0351 Figure 82. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0) 1. Parameters: P1: sequence of 1 conversion, hardware trigger 1 P2: sequence of 1 conversion, hardware trigger 1 P3: sequence of 1 conversion, hardware trigger 1 Figure 83.
Page 461: Table 90. Tsar Timings Depending On Resolution
RM0351 Analog-to-digital converters (ADC) 16.3.22 Programmable resolution (RES) - fast conversion mode It is possible to perform faster conversion by reducing the ADC resolution. The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the control bits RES[1:0].
Page 462: Figure 84. Single Conversions Of A Sequence, Software Trigger
Analog-to-digital converters (ADC) RM0351 16.3.25 Timing diagrams example (single/continuous modes, hardware/software triggers) Figure 84. Single conversions of a sequence, software trigger 1. EXTEN=0x0, CONT=0 2. Channels selected = 1,9, 10, 17; AUTDLY=0. Figure 85. Continuous conversion of a sequence, software trigger 1.
Page 463: Figure 86. Single Conversions Of A Sequence, Hardware Trigger
RM0351 Analog-to-digital converters (ADC) Figure 86. Single conversions of a sequence, hardware trigger 1. TRGx (over-frequency) is selected as trigger source, EXTEN = 01, CONT = 0 2. Channels selected = 1, 2, 3, 4; AUTDLY=0. Figure 87. Continuous conversions of a sequence, hardware trigger 1.
Page 464: Table 91. Offset Computation Versus Data Resolution
Analog-to-digital converters (ADC) RM0351 Special case: when left-aligned, the data are aligned on a half-word basis except when the resolution is set to 6-bit. In that case, the data are aligned on a byte basis as shown in Figure 90 Figure Note: Left-alignment is not supported in oversampling mode.
Page 465: Figure 88. Right Alignment (Offset Disabled, Unsigned Value)
RM0351 Analog-to-digital converters (ADC) Figure 88. Right alignment (offset disabled, unsigned value) Figure 89. Right alignment (offset enabled, signed value) DocID024597 Rev 3 465/1693...
Page 466: Figure 90. Left Alignment (Offset Disabled, Unsigned Value)
Analog-to-digital converters (ADC) RM0351 Figure 90. Left alignment (offset disabled, unsigned value) Figure 91. Left alignment (offset enabled, signed value) 466/1693 DocID024597 Rev 3...
Page 467: Figure 92. Example Of Overrun (Ovr)
RM0351 Analog-to-digital converters (ADC) ADC overrun (OVR, OVRMOD) The overrun flag (OVR) notifies of a buffer overrun event, when the regular converted data was not read (by the CPU or the DMA) before new converted data became available. The OVR flag is set if the EOC flag is still 1 at the time when a new conversion completes. An interrupt can be generated if bit OVRIE=1.
Page 468 Analog-to-digital converters (ADC) RM0351 Managing conversions without using the DMA and without overrun It may be useful to let the ADC convert one or more channels without reading the data each time (if there is an analog watchdog for instance). In this case, the OVRMOD bit must be configured to 1 and OVR flag should be ignored by the software.
Page 469: Dynamic Low-Power Features
RM0351 Analog-to-digital converters (ADC) DMA circular mode (DMACFG=1) In this mode, the ADC generates a DMA transfer request each time a new conversion data is available in the data register, even if the DMA has reached the last DMA transfer. This allows configuring the DMA in circular mode to handle a continuous analog input data stream.
Page 470: Figure 93. Autodly=1, Regular Conversion In Continuous Mode, Software Trigger
Analog-to-digital converters (ADC) RM0351 Wait until JEOS=1 (no more conversions are restarted) Clear JEOS, Set ADSTP=1 Read the regular data. If this procedure is not respected, a new regular sequence can re-start if JEOS is cleared after ADSTP has been set. In AUTDLY mode, a hardware regular trigger event is ignored if it occurs during an already ongoing regular sequence or during the delay that follows the last regular conversion of the sequence.
Page 471: Figure 94. Autodly=1, Regular Hw Conversions Interrupted By Injected Conversions
RM0351 Analog-to-digital converters (ADC) Figure 94. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=0; JDISCEN=0) 1. AUTDLY=1 2. Regular configuration: EXTEN=0x1 (HW trigger), CONT=0, DISCEN=0, CHANNELS = 1, 2, 3 3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=0, CHANNELS = 5,6 DocID024597 Rev 3 471/1693...
Page 472: (Discen=1, Jdiscen=1)
Analog-to-digital converters (ADC) RM0351 Figure 95. AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=1, JDISCEN=1) 1. AUTDLY=1 2. Regular configuration: EXTEN=0x1 (HW trigger), CONT=0, DISCEN=1, DISCNUM=1, CHANNELS = 1, 2, 3. 3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=1, CHANNELS = 5,6 472/1693 DocID024597 Rev 3...
Page 473: Figure 96. Autodly=1, Regular Continuous Conversions Interrupted By Injected Conversions
RM0351 Analog-to-digital converters (ADC) Figure 96. AUTODLY=1, regular continuous conversions interrupted by injected conversions 1. AUTDLY=1 2. Regular configuration: EXTEN=0x0 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2, 3 3. Injected configuration: JEXTEN=0x1 (HW Trigger), JDISCEN=0, CHANNELS = 5,6 Figure 97. AUTODLY=1 in auto- injected mode (JAUTO=1) 1.
Page 474: Table 92. Analog Watchdog Channel Selection
Analog-to-digital converters (ADC) RM0351 16.3.28 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) The three AWD analog watchdogs monitor whether some channels remain within a configured voltage range (window). Figure 98. Analog watchdog’s guarded area AWDx flag and interrupt An interrupt can be enabled for each of the 3 analog watchdogs by setting AWDxIE in the ADCx_IER register (x=1,2,3).
Page 475: Table 93. Analog Watchdog 1 Comparison
RM0351 Analog-to-digital converters (ADC) These thresholds are programmed in bits HT1[11:0] and LT1[11:0] of the ADCx_TR1 register for the analog watchdog 1. When converting data with a resolution of less than 12 bits (according to bits RES[1:0]), the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned).
Page 476: Figure 99. Adcy_Awdx_Out Signal Generation (On All Regular Channels)
Analog-to-digital converters (ADC) RM0351 ADCy_AWDx_OUT signal output generation Each analog watchdog is associated to an internal hardware signal ADCy_AWDx_OUT (y=ADC number, x=watchdog number) which is directly connected to the ETR input (external trigger) of some on-chip timers. Refer to the on-chip timers section to understand how to select the ADCy_AWDx_OUT signal as ETR.
Page 477: Figure 100. Adcy_Awdx_Out Signal Generation (Awdx Flag Not Cleared By Sw)
RM0351 Analog-to-digital converters (ADC) Figure 100. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by SW) Figure 101. ADCy_AWDx_OUT signal generation (on a single regular channel) Figure 102. ADCy_AWDx_OUT signal generation (on all injected channels) DocID024597 Rev 3 477/1693...
Page 478: Figure 103. 20-Bit To 16-Bit Result Truncation
Analog-to-digital converters (ADC) RM0351 16.3.29 Oversampler The oversampling unit performs data pre-processing to offload the CPU. It is able to handle multiple conversions and average them into a single data with increased data width, up to 16-bit. It provides a result with the following form, where N and M can be adjusted: –...
Page 479: Table 95. Maximum Output Results Versus N And M (Gray Cells Indicate Truncation)
RM0351 Analog-to-digital converters (ADC) Table 95. Maximum output results versus N and M (gray cells indicate truncation) No-shift 1-bit 2-bit 3-bit 4-bit 5-bit 6-bit 7-bit 8-bit Over shift shift shift shift shift shift shift shift sampling Raw data OVSS = OVSS = OVSS = OVSS =...
Page 480: Figure 105. Triggered Regular Oversampling Mode (Trovs Bit = 1)
Analog-to-digital converters (ADC) RM0351 Analog watchdog The analog watchdog functionality is maintained (AWDSGL and AWDEN bits), with the following difference: – the RES[1:0] bits are ignored, comparison is always done on using the full 12-bit values HT[11:0] and LT[11:0] – the comparison is performed on the most significant 12-bit of the 16-bit oversampled results ADCx_DR[15:4] Note:...
Page 481: Figure 106. Regular Oversampling Modes (4X Ratio)
RM0351 Analog-to-digital converters (ADC) Oversampling regular channels only The regular oversampling mode bit ROVSM defines how the regular oversampling sequence is resumed if it is interrupted by injected conversion: – in continued mode, the accumulation re-starts from the last valid data (prior to the conversion abort request due to the injected trigger).
Page 482: Figure 107. Regular And Injected Oversampling Modes Used Simultaneously
Analog-to-digital converters (ADC) RM0351 Figure 107 below. Figure 107. Regular and injected oversampling modes used simultaneously Triggered regular oversampling with injected conversions It is possible to have triggered regular mode with injected conversions. In this case, the injected mode oversampling mode must be disabled, and the ROVSM bit is ignored (resumed mode is forced).
Page 483: Table 96. Oversampler Operating Modes Summary
RM0351 Analog-to-digital converters (ADC) Figure 109. Oversampling in auto-injected mode It is possible to have also the triggered mode enabled, using the TROVS bit. In this case, the ADC must be configured as following: JAUTO = 1, DISCEN = 0, JDISCEN = 0, ROVSE = 1, JOVSE = 1 and TROVSE = 1.
Page 484 Analog-to-digital converters (ADC) RM0351 Four possible modes are implemented: • Injected simultaneous mode • Regular simultaneous mode • Interleaved mode • Alternate trigger mode It is also possible to use these modes combined in the following ways: • Injected simultaneous mode + Regular simultaneous mode •...
Page 485: Figure 110. Dual Adc Block Diagram (1)
RM0351 Analog-to-digital converters (ADC) Figure 110. Dual ADC block diagram External triggers also exist on slave ADC but are not shown for the purposes of this diagram. The ADC common data register (ADCx_CDR) contains both the master and slave ADC regular converted data. DocID024597 Rev 3 485/1693...
Page 486: Figure 111. Injected Simultaneous Mode On 4 Channels: Dual Adc Mode
Analog-to-digital converters (ADC) RM0351 Injected simultaneous mode This mode is selected by programming bits DUAL[4:0]=00101 This mode converts an injected group of channels. The external trigger source comes from the injected group multiplexer of the master ADC (selected by the JEXTSEL[3:0] bits in the ADCx_JSQR register).
Page 487 RM0351 Analog-to-digital converters (ADC) ongoing regular sequence and the associated delay phases are ignored. There is the same behavior for regular sequences occurring on the slave ADC. Regular simultaneous mode with independent injected This mode is selected by programming bits DUAL[4:0] = 00110. This mode is performed on a regular group of channels.
Page 488: Figure 112. Regular Simultaneous Mode On 16 Channels: Dual Adc Mode
Analog-to-digital converters (ADC) RM0351 Note: In MDMA mode (MDMA[1:0]=0b10 or 0b11), the user must program the same number of conversions in the master’s sequence as in the slave’s sequence. Otherwise, the remaining conversions will not generate a DMA request. Figure 112. Regular simultaneous mode on 16 channels: dual ADC mode If DISCEN=1 then each “n”...
Page 489 RM0351 Analog-to-digital converters (ADC) The minimum delay which separates 2 conversions in interleaved mode is configured in the DELAY bits in the ADCx_CCR register. This delay starts to count after the end of the sampling phase of the master conversion. This way, an ADC cannot start a conversion if the complementary ADC is still sampling its input (only one ADC can sample the input signal at a given time).
Page 490: Figure 113. Interleaved Mode On 1 Channel In Continuous Conversion Mode: Dual Adc Mode
Analog-to-digital converters (ADC) RM0351 Figure 113. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode Figure 114. Interleaved mode on 1 channel in single conversion mode: dual ADC mode If DISCEN=1, each “n” simultaneous conversions (“n” is defined by DISCNUM) of the regular sequence require a regular trigger event to occur.
Page 491: Figure 115. Interleaved Conversion With Injection
RM0351 Analog-to-digital converters (ADC) Figure 115. Interleaved conversion with injection Alternate trigger mode This mode is selected by programming bits DUAL[4:0] = 01001. This mode can be started only on an injected group. The source of external trigger comes from the injected group multiplexer of the master ADC. This mode is only possible when selecting hardware triggers: JEXTEN must not be 0x0.
Page 492: Figure 116. Alternate Trigger: Injected Group Of Each Adc
Analog-to-digital converters (ADC) RM0351 Figure 116. Alternate trigger: injected group of each ADC Note: Regular conversions can be enabled on one or all ADCs. In this case the regular conversions are independent of each other. A regular conversion is interrupted when the ADC has to perform an injected conversion.
Page 493: Figure 117. Alternate Trigger: 4 Injected Channels (Each Adc) In Discontinuous Mode
RM0351 Analog-to-digital converters (ADC) Figure 117. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode Combined regular/injected simultaneous mode This mode is selected by programming bits DUAL[4:0] = 00001. It is possible to interrupt the simultaneous conversion of a regular group to start the simultaneous conversion of an injected group.
Page 494: Figure 118. Alternate + Regular Simultaneous
Analog-to-digital converters (ADC) RM0351 Figure 118. Alternate + regular simultaneous If a trigger occurs during an injected conversion that has interrupted a regular conversion, the alternate trigger is served. Figure 119 shows the behavior in this case (note that the 6th trigger is ignored because the associated alternate conversion is not complete).
Page 495: Figure 120. Interleaved Single Channel Ch0 With Injected Sequence Ch11, Ch12
RM0351 Analog-to-digital converters (ADC) Figure 120. Interleaved single channel CH0 with injected sequence CH11, CH12 Figure 121. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 1: Master interrupted first Figure 122. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12 - case 2: Slave interrupted first DMA requests in dual ADC mode In all dual ADC modes, it is possible to use two DMA channels (one for the master, one for...
Page 496: Figure 123. Dma Requests In Regular Simultaneous Mode When Mdma=0B00
Analog-to-digital converters (ADC) RM0351 regular simultaneous mode when MDMA=0b00). Figure 123. DMA Requests in regular simultaneous mode when MDMA=0b00 In simultaneous regular and interleaved modes, it is also possible to save one DMA channel and transfer both data using a single DMA channel. For this MDMA bits must be configured in the ADCx_CCR register: •...
Page 497: Figure 124. Dma Requests In Regular Simultaneous Mode When Mdma=0B10
RM0351 Analog-to-digital converters (ADC) Figure 124. DMA requests in regular simultaneous mode when MDMA=0b10 Figure 125. DMA requests in interleaved mode when MDMA=0b10 DocID024597 Rev 3 497/1693...
Page 498: Temperature Sensor
Analog-to-digital converters (ADC) RM0351 Note: When using MDMA mode, the user must take care to configure properly the duration of the master and slave conversions so that a DMA request is generated and served for reading both data (master + slave) before a new conversion is available. •...
Page 499: Figure 126. Temperature Sensor Channel Block Diagram
The user application can then read them and use them to improve the accuracy of the temperature sensor or the internal reference. Refer to the STM32L4x6 datasheet for additional information. Main features •...
Page 500: Figure 127. Vbat Channel Block Diagram
Analog-to-digital converters (ADC) RM0351 Calculate the actual temperature using the following formula: 110 °C 30 °C – --------------------------------------------------------- - Temperature in °C × TS_DATA TS_CAL1 30 °C – TS_CAL2 TS_CAL1 – Where: • TS_CAL2 is the temperature sensor calibration value acquired at 110°C •...
Page 501: Figure 128. Vrefint Channel Block Diagram
The internal voltage reference is internally connected to the input channel 0 of the ADC1 (ADC1_IN0). Refer to the electrical characteristics section of the STM32L4x6 datasheet for the sampling time value to be applied when converting the internal voltage reference voltage.
Page 502: Table 97. Adc Interrupts Per Each Adc
Analog-to-digital converters (ADC) RM0351 actual VDDA voltage using the internal reference voltage, resulting in the following formula: × × 3.0 V VREFINT_CAL ADCx_DATA ------------------------------------------------------------------------------------------------------- - CHANNELx × VREFINT_DATA FULL_SCALE Where: • VREFINT_CAL is the VREFINT calibration value • ADCx_DATA is the value measured by the ADC on channel x (right-aligned) •...
Page 503: Adc Registers (For Each Adc)
RM0351 Analog-to-digital converters (ADC) 16.5 ADC registers (for each ADC) Refer to Section 1.1 on page 61 for a list of abbreviations used in register descriptions. 16.5.1 ADC interrupt and status register (ADCx_ISR) Address offset: 0x00 Reset value: 0x0000 0000 Res.
Page 504 Analog-to-digital converters (ADC) RM0351 Bit 5 JEOC: Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADCx_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADCx_JDRy register 0: Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)
Page 505: Adc Interrupt Enable Register (Adcx_Ier)
RM0351 Analog-to-digital converters (ADC) 16.5.2 ADC interrupt enable register (ADCx_IER) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AWD3 AWD2 AWD1 EOSMP ADRDY Res. Res. Res.
Page 506 Analog-to-digital converters (ADC) RM0351 Bit 5 JEOCIE: End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. 0: JEOC interrupt disabled. 1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set. Note: Software is allowed to write this bit only when JADSTART=0 (which ensures that no regular conversion is ongoing).
Page 507: Adc Control Register (Adcx_Cr)
RM0351 Analog-to-digital converters (ADC) 16.5.3 ADC control register (ADCx_CR) Address offset: 0x08 Reset value: 0x2000 0000 ADCA DEEP ADVREG Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LDIF Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 508 Analog-to-digital converters (ADC) RM0351 Bit 5 JADSTP: ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured.
Page 509 RM0351 Analog-to-digital converters (ADC) Bit 2 ADSTART: ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion will start immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration).
Page 510: Adc Configuration Register (Adcx_Cfgr)
Analog-to-digital converters (ADC) RM0351 16.5.4 ADC configuration register (ADCx_CFGR) Address offset: 0x0C Reset value: 0x8000 0000 JAWD1 AWD1 AWD1S JDISC DISC JQDIS AWD1CH[4:0] JAUTO DISCNUM[2:0] Res. CONT EXTEN[1:0] EXTSEL[3:0] ALIGN RES[1:0] Res. Bit 31 JQDIS: Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism : 0: Injected Queue enabled 1: Injected Queue disabled Note: Software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures...
Page 511 RM0351 Analog-to-digital converters (ADC) Bit 23 AWD1EN: Analog watchdog 1 enable on regular channels This bit is set and cleared by software 0: Analog watchdog 1 disabled on regular channels 1: Analog watchdog 1 enabled on regular channels Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing).
Page 512 Analog-to-digital converters (ADC) RM0351 Bit 16 DISCEN: Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. 0: Discontinuous mode for regular channels disabled 1: Discontinuous mode for regular channels enabled Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1.
Page 513 RM0351 Analog-to-digital converters (ADC) Bits 9:6 EXTSEL[3:0]: External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: 0000: Event 0 0001: Event 1 0010: Event 2 0011: Event 3 0100: Event 4 0101: Event 5 0110: Event 6...
Page 514: Adc Configuration Register 2 (Adcx_Cfgr2)
Analog-to-digital converters (ADC) RM0351 16.5.5 ADC configuration register 2 (ADCx_CFGR2) Address offset: 0x10 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TROVS OVSS[3:0] OVSR[2:0] JOVSE ROVSE Bits 31:11 Reserved, must be kept at reset value.
Page 515: Adc Sample Time Register 1 (Adcx_Smpr1)
RM0351 Analog-to-digital converters (ADC) Bits 4:2 OVSR[2:0]: Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x 101: 64x 110: 128x 111: 256x Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing).
Page 516 Analog-to-digital converters (ADC) RM0351 Bits 31:30 Reserved, must be kept at reset value. Bits 29:0 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. 000: 2.5 ADC clock cycles 001: 6.5 ADC clock cycles 010: 12.5 ADC clock cycles...
Page 517: Adc Sample Time Register 2 (Adcx_Smpr2)
RM0351 Analog-to-digital converters (ADC) 16.5.7 ADC sample time register 2 (ADCx_SMPR2) Address offset: 0x18 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. SMP18[2:0] SMP17[2:0] SMP16[2:0] SMP15[2:1] SMP15_0 SMP14[2:0] SMP13[2:0] SMP12[2:0] SMP11[2:0] SMP10[2:0] Bits 31:27 Reserved, must be kept at reset value. Bits 26:0 SMPx[2:0]: Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel.
Page 518: Adc Watchdog Threshold Register 2 (Adcx_Tr2)
Analog-to-digital converters (ADC) RM0351 Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to Section 16.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: Software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing).
Page 519: Adc Watchdog Threshold Register 3 (Adcx_Tr3)
RM0351 Analog-to-digital converters (ADC) 16.5.10 ADC watchdog threshold register 3 (ADCx_TR3) Address offset: 0x28 Reset value: 0x00FF 0000 Res. Res. Res. Res. Res. Res. Res. Res. HT3[7:0] Res. Res. Res. Res. Res. Res. Res. Res. LT3[7:0] Bits 31:24 Reserved, must be kept at reset value. Bits 23:16 HT3[7:0]: Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3.
Page 520: Adc Regular Sequence Register 1 (Adcx_Sqr1)
Analog-to-digital converters (ADC) RM0351 16.5.11 ADC regular sequence register 1 (ADCx_SQR1) Address offset: 0x30 Reset value: 0x0000 0000 Res. Res. Res. SQ4[4:0] Res. SQ3[4:0] Res. SQ2[4] SQ2[3:0] Res. SQ1[4:0] Res. Res. L[3:0] Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ4[4:0]: 4th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 4th in the regular conversion sequence.
Page 521: Adc Regular Sequence Register 2 (Adcx_Sqr2)
RM0351 Analog-to-digital converters (ADC) 16.5.12 ADC regular sequence register 2 (ADCx_SQR2) Address offset: 0x34 Reset value: 0x0000 0000 Res. Res. Res. SQ9[4:0] Res. SQ8[4:0] Res. SQ7[4] SQ7[3:0] Res. SQ6[4:0] Res. SQ5[4:0] Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ9[4:0]: 9th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 9th in the regular conversion sequence.
Page 522: Adc Regular Sequence Register 3 (Adcx_Sqr3)
Analog-to-digital converters (ADC) RM0351 16.5.13 ADC regular sequence register 3 (ADCx_SQR3) Address offset: 0x38 Reset value: 0x0000 0000 Res. Res. Res. SQ14[4:0] Res. SQ13[4:0] Res. SQ12[4] SQ12[3:0] Res. SQ11[4:0] Res. SQ10[4:0] Bits 31:29 Reserved, must be kept at reset value. Bits 28:24 SQ14[4:0]: 14th conversion in regular sequence These bits are written by software with the channel number (0..18) assigned as the 14th in the regular conversion sequence.
Page 523: Adc Regular Sequence Register 4 (Adcx_Sqr4)
RM0351 Analog-to-digital converters (ADC) 16.5.14 ADC regular sequence register 4 (ADCx_SQR4) Address offset: 0x3C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SQ16[4:0] Res.
Page 524: Adc Regular Data Register (Adcx_Dr)
Analog-to-digital converters (ADC) RM0351 16.5.15 ADC regular Data Register (ADCx_DR) Address offset: 0x40 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RDATA[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 RDATA[15:0]: Regular Data converted These bits are read-only.
Page 525: Adc Injected Sequence Register (Adcx_Jsqr)
RM0351 Analog-to-digital converters (ADC) 16.5.16 ADC injected sequence register (ADCx_JSQR) Address offset: 0x4C Reset value: 0x0000 0000 Res. JSQ4[4:0] Res. JSQ3[4:0] Res. JSQ2[4:2] JSQ2[1:0] Res. JSQ1[4:0] JEXTEN[1:0] JEXTSEL[3:0] JL[1:0] Bit 31 Reserved, must be kept at reset value. Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence These bits are written by software with the channel number (0..18) assigned as the 4th in the injected conversion sequence.
Page 526 Analog-to-digital converters (ADC) RM0351 Bits 7:6 JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. 00: If JQDIS=0 (queue enabled), Hardware and software trigger detection disabled 00: If JQDIS=1 (queue disabled), Hardware trigger detection disabled (conversions can be launched by software) 01: Hardware trigger detection on the rising edge...
Page 527: Adc Offset Register (Adcx_Ofry) (Y=1..4)
RM0351 Analog-to-digital converters (ADC) 16.5.17 ADC offset register (ADCx_OFRy) (y=1..4) Address offset: 0x60, 0x64, 0x68, 0x6C Reset value: 0x0000 0000 OFFSETy OFFSETy_CH[4:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OFFSETy[11:0] Bit 31 OFFSETy_EN: Offset y Enable This bit is written by software to enable or disable the offset programmed into bits OFFSETy[11:0].
Page 528: Adc Injected Data Register (Adcx_Jdry, Y= 1..4)
Analog-to-digital converters (ADC) RM0351 16.5.18 ADC injected data register (ADCx_JDRy, y= 1..4) Address offset: 0x80 - 0x8C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. JDATA[15:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 JDATA[15:0]: Injected data These bits are read-only.
Page 529: Adc Analog Watchdog 3 Configuration Register (Adcx_Awd3Cr)
RM0351 Analog-to-digital converters (ADC) 16.5.20 ADC Analog Watchdog 3 Configuration Register (ADCx_AWD3CR) Address offset: 0xA4 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AWD3CH[18:16] AWD3CH[15:0] Bits 31:19 Reserved, must be kept at reset value. Bits 18:0 AWD2CH[18:0]: Analog watchdog 2 channel selection These bits are set and cleared by software.
Page 530: Adc Calibration Factors (Adcx_Calfact)
Analog-to-digital converters (ADC) RM0351 Bits 31:19 Reserved, must be kept at reset value. Bits 18:16 DIFSEL[18:16]: Differential mode for channels 18 to 16. These bits are read only. These channels are forced to single-ended input mode (either connected to a single-ended I/O port or to an internal channel). Bits 15:1 DIFSEL[15:1]: Differential mode for channels 15 to 1 These bits are set and cleared by software.
Page 531 RM0351 Analog-to-digital converters (ADC) Bits 22:16 CALFACT_D[6:0]: Calibration Factors in differential mode These bits are written by hardware or by software. Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new differential calibration is launched.
Page 532: Adc Common Registers
Analog-to-digital converters (ADC) RM0351 16.6 ADC common registers These registers define the control and status registers common to master and slave ADCs: 16.6.1 ADC Common status register (ADCx_CSR) Address offset: 0x00 (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 This register provides an image of the status bits of the different ADCs.
Page 533 RM0351 Analog-to-digital converters (ADC) Bit 16 ADRDY_SLV: Slave ADC ready This bit is a copy of the ADRDY bit in the corresponding ADCx_ISR register. Bits 15:11 Reserved, must be kept at reset value. Bit 10 JQOVF_MST: Injected Context Queue Overflow flag of the master ADC This bit is a copy of the JQOVF bit in the corresponding ADCx_ISR register.
Page 534: Adc Common Control Register (Adcx_Ccr)
Analog-to-digital converters (ADC) RM0351 16.6.2 ADC common control register (ADCx_CCR) Address offset: 0x08 (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 CH18 CH17 VREF Res. Res. Res. Res. Res. Res. Res. PRESC[3:0] CKMODE[1:0] MDMA[1:0]...
Page 535 RM0351 Analog-to-digital converters (ADC) Bits 21:18 PRESC[3:0]: ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. 0000: input ADC clock not divided 0001: input ADC clock divided by 2 0010: input ADC clock divided by 4 0011: input ADC clock divided by 6...
Page 536: Table 98. Delay Bits Versus Adc Resolution
Analog-to-digital converters (ADC) RM0351 Bits 11:8 DELAY: Delay between 2 sampling phases These bits are set and cleared by software. These bits are used in dual interleaved modes. Refer to Table 98 for the value of ADC resolution versus DELAY bits values. Note: Software is allowed to write these bits only when the ADCs are disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Page 537: Table 99. Adc Global Register Map
RM0351 Analog-to-digital converters (ADC) 16.6.3 ADC common regular data register for dual mode (ADCx_CDR) Address offset: 0x0C (this offset address is relative to the master ADC base address + 0x300) Reset value: 0x0000 0000 RDATA_SLV[15:0] RDATA_MST[15:0] Bits 31:16 RDATA_SLV[15:0]: Regular data of the slave ADC In dual mode, these bits contain the regular data of the slave ADC.
Page 538: Table 100. Adc Register Map And Reset Values For Each Adc
Analog-to-digital converters (ADC) RM0351 Table 100. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) Offset Register ADCx_ISR 0x00 Reset value ADCx_IER 0x04 Reset value ADCx_CR 0x08 Reset value DISCNUM EXTSEL ADCx_CFGR AWD1CH[4:0] [2:0] [3:0]...
Page 539 RM0351 Analog-to-digital converters (ADC) Table 100. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) (continued) Offset Register JEXTSEL ADCx_JSQR JSQ4[4:0] JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] JL[1:0] [3:0] 0x4C Reset value 0x50- Reserved Res. 0x5C OFFSET1_ ADCx_OFR1...
Page 540: Common Registers) Offset =0X300)
Analog-to-digital converters (ADC) RM0351 Table 100. ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) (continued) Offset Register ADCx_CALFACT CALFACT_D[6:0] CALFACT_S[6:0] 0xB4 Reset value Table 101. ADC register map and reset values (master and slave ADC common registers) offset =0x300) Offset Register...
Page 541: Introduction
RM0351 Digital-to-analog converter (DAC) Digital-to-analog converter (DAC) 17.1 Introduction The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned.
Page 542: Dac Functional Description
Digital-to-analog converter (DAC) RM0351 17.3 DAC functional description 17.3.1 DAC block diagram Figure 129. DAC channel block diagram 1. The output mode controller switch between the normal mode in buffer/unbuffer configuration and the sample&hold mode The DAC includes : • Two output channels •...
Page 543: Table 102. Dac Pins
RM0351 Digital-to-analog converter (DAC) Table 102. DAC pins Name Signal type Remarks Input, analog reference The higher/positive reference voltage for the DAC, REF+ ≤ ≤ positive (refer to datasheet) DDAmin REF+ Input, analog supply Analog power supply Input, analog supply ground Ground for analog power supply DAC_OUTx Analog output signal...
Page 544: Figure 130. Data Registers In Single Dac Channel Mode
Digital-to-analog converter (DAC) RM0351 Figure 130. Data registers in single DAC channel mode 8-bit right aligned 12-bit left aligned 12-bit right aligned ai14710 • Dual DAC channels, there are three possibilities: – 8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD [7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits) –...
Page 545: Figure 132. Timing Diagram For Conversion With Trigger Disabled Ten = 0
RM0351 Digital-to-analog converter (DAC) Figure 132. Timing diagram for conversion with trigger disabled TEN = 0 APB1_CLK 0x1AC Output voltage 0x1AC available on DAC_OUT pin SETTLING ai14711b 17.3.5 DAC output voltage Digital inputs are converted to output voltages on a linear conversion between 0 and V REF+ The analog output voltages on each DAC channel pin are determined by the following equation:...
Page 546: Figure 133. Dac Lfsr Register Calculation Algorithm
Digital-to-analog converter (DAC) RM0351 DMA underrun The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgement for the first external trigger is received (first request), then no new request is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set, reporting the error condition.
Page 547: Figure 134. Dac Conversion (Sw Trigger Enabled) With Lfsr Wave Generation
RM0351 Digital-to-analog converter (DAC) Figure 134. DAC conversion (SW trigger enabled) with LFSR wave generation APB1_CLK 0x00 0xAAA 0xD55 SWTRIG ai14714 Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register. 17.3.9 Triangle-wave generation It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.
Page 548: Figure 136. Dac Conversion (Sw Trigger Enabled) With Triangle Wave Generation
Digital-to-analog converter (DAC) RM0351 Figure 136. DAC conversion (SW trigger enabled) with triangle wave generation APB1_CLK 0xABE 0xABE 0xABF 0xAC0 SWTRIG ai14714 Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register. The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed.
Page 549: Table 103. Sample And Refresh Timings
RM0351 Digital-to-analog converter (DAC) The sample/hold mode operations can be divided into 3 phases: Sample phase: the sample/hold element is charged to the desired voltage. The charging time depends on capacitor value (internal or external, selected by the user). The sampling time is configured with the TSAMx[9:0] bits in DAC_SHSRx register. During the write of the TSAMx[9:0] bits;...
Page 550: Figure 137. Dac Sample And Hold Mode Phases Diagram
Digital-to-analog converter (DAC) RM0351 Refresh phase: = 7 μs + (2000 * 100 * 10 ) * ln(2*10) = 606.1 μs refresh (where N = 10 (10 LSB drop during the hold phase) Hold phase: = 0.0073 V (10 LSB of 12bit at 3 V) leak hold load...
Page 551: Table 104. Channel Output Modes Summary
RM0351 Digital-to-analog converter (DAC) Table 104. Channel output modes summary MODEx[2:0] Mode Buffer Output connections Connected to external pin Enabled Connected to external pin and to on chip-peripherals (ex, comparators) Normal mode Connected to external pin Disabled Connected to on chip peripherals (ex, comparators) Connected to external pin Enabled Connected to external pin and to on chip peripherals (ex, comparators)
Page 552 Digital-to-analog converter (DAC) RM0351 Note: Refer to the datasheet for more details of the Nominal factory trimming conditions Note: Also, when VDD/VDDA is removed (exemple the MCU enters in STANDBY or VBAT modes) the calibration is required. 552/1693 DocID024597 Rev 3...
Page 553: Dual Dac Channel Conversion
RM0351 Digital-to-analog converter (DAC) The steps to perform a user trimming calibration are as below: If the DAC channel is active, Write 0 to ENx bit in DAC_CR to disable the channel. Select a mode where the buffer is enabled, by writing to DACx_MCR register, MODEx[2:0] = 000b or 001b or 100b or 101b, Write DACx_DHR12Rx[11:0] with the middle code: 0x800 value, Start the DAC channelx calibration, by setting the CENx bit in DACx_CR register to 1,...
Page 554 Digital-to-analog converter (DAC) RM0351 When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1 (three APB1 clock cycles later). When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2 (three APB1 clock cycles later). Independent trigger with single LFSR generation To configure the DAC in this conversion mode, the following sequence is required: •...
Page 555 RM0351 Digital-to-analog converter (DAC) Independent trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure different trigger sources by setting different values in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 556 Digital-to-analog converter (DAC) RM0351 Simultaneous trigger without wave generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 557: Table 105. Effect Of Low-Power Modes On Dac
RM0351 Digital-to-analog converter (DAC) Simultaneous trigger with single triangle generation To configure the DAC in this conversion mode, the following sequence is required: • Set the two DAC channel trigger enable bits TEN1 and TEN2 • Configure the same trigger source for both DAC channels by setting the same value in the TSEL1[2:0] and TSEL2[2:0] bits •...
Page 558 Digital-to-analog converter (DAC) RM0351 Table 105. Effect of low-power modes on DAC (continued) Mode Description Standby The DAC peripheral is powered down and must be reinitialized after exiting Standby or Shutdown mode. Shutdown 558/1693 DocID024597 Rev 3...
Page 559: Dac Registers
RM0351 Digital-to-analog converter (DAC) 17.5 DAC registers Refer to Section 1 on page 61 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 17.5.1 DAC control register (DAC_CR) Address offset: 0x00 Reset value: 0x0000 0000 DMAU Res.
Page 560 Digital-to-analog converter (DAC) RM0351 Bits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 00: wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 000: Timer 6 TRGO event...
Page 561 RM0351 Digital-to-analog converter (DAC) Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15...
Page 562: Dac Software Trigger Register (Dac_Swtrgr)
Digital-to-analog converter (DAC) RM0351 17.5.2 DAC software trigger register (DAC_SWTRGR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 563 RM0351 Digital-to-analog converter (DAC) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC1DHR[11:0] Res. Res. Res. Res. Bits 31:16 Reserved, must be kept at reset value. Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
Page 564 Digital-to-analog converter (DAC) RM0351 17.5.7 DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) Address offset: 0x18 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC2DHR[11:0] Res. Res. Res.
Page 565 RM0351 Digital-to-analog converter (DAC) Bits 31:28 Reserved, must be kept at reset value. Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. Bits 15:12 Reserved, must be kept at reset value. Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
Page 566: Dac Channel1 Data Output Register (Dac_Dor1)
Digital-to-analog converter (DAC) RM0351 17.5.11 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) Address offset: 0x28 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DACC2DHR[7:0] DACC1DHR[7:0] Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
Page 567: Dac Status Register (Dac_Sr)
RM0351 Digital-to-analog converter (DAC) Bits 31:12 Reserved, must be kept at reset value. Bits 11:0 DACC2DOR[11:0]: DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. 17.5.14 DAC status register (DAC_SR) Address offset: 0x34 Reset value: 0x0000 0000 CAL_ DMAU BWST2...
Page 568: Dac Calibration Control Register (Dac_Ccr)
Digital-to-analog converter (DAC) RM0351 Bit 14 CAL_FLAG1: DAC Channel 1 calibration offset status This bit is set and cleared by hardware 0: calibration trimming value is greater than the offset correction value 1: calibration trimming value is lower than the offset correction value Bit 13 DMAUDR1: DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
Page 569: Dac Sample And Hold Sample Time Register 1 (Dac_Shsr1)
RM0351 Digital-to-analog converter (DAC) Bits 31:19 Reserved, must be kept at reset value. Bits 18:16 MODE2[2:0]: DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored.
Page 570: Dac Sample And Hold Sample Time Register 2 (Dac_Shsr2)
Digital-to-analog converter (DAC) RM0351 Res. Res. Res. Res. Res. Res. TSAMPLE1[9:0] Bits 31:10 Reserved, must be kept at reset value. Bits 9:0 TSAMPLE1[9:0]: DAC Channel 1 sample Time (only valid in sample & hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored.
Page 571: Dac Sample And Hold Refresh Time Register (Dac_Shrr)
RM0351 Digital-to-analog converter (DAC) Bits 31:26 Reserved, must be kept at reset value. Bits 25:16 THOLD2[9:0]: DAC Channel 2 hold time (only valid in sample & hold mode). Hold time= (THOLD[9:0] ) x T LSI Bits 15:10 Reserved, must be kept at reset value. Bits 9:0 THOLD1[9:0]: DAC Channel 1 hold Time (only valid in sample &...
Page 572: Table 106. Dac Register Map
Digital-to-analog converter (DAC) RM0351 17.5.21 DAC register map Table 106 summarizes the DAC registers. Table 106. DAC register map Offset Register TSEL2 TSEL1 DAC_CR MAMP2[3:0] MAMP1[3:0] [2:0] [2:0] 0x00 Reset value DAC_ SWTRGR 0x04 Reset value DAC_ DACC1DHR[11:0] DHR12R1 0x08 Reset value DAC_ DACC1DHR[11:0]...
Page 573 RM0351 Digital-to-analog converter (DAC) Table 106. DAC register map Offset Register DAC_CCR OTRIM2[4:0] OTRIM1[4:0] 0x38 Reset value X X X X MODE2 MODE1 DAC_MCR [2:0] [2:0] 0x3C Reset value DAC_SHSR1 TSAMPLE1[9:0] 0x40 Reset value DAC_SHSR2 TSAMPLE2[9:0] 0x44 Reset value DAC_SHHR THOLD2[9:0] THOLD1[9:0] 0x48...
Page 574: Table 107. Vrefbuf Buffer Modes
18.1 Introduction The STM32L4x6 devices embed a voltage reference buffer which can be used as voltage reference for ADCs, DACs and also as voltage reference for external components through the VREF+ pin. When the VREF+ is double-bonded with VDDA in a package, the voltage reference buffer is not available and must be kept disable (refer to datasheet for packages pinout description).
Page 575: Vrefbuf Calibration Control Register (Vrefbuf_Ccr)
RM0351 Voltage reference buffer (VREFBUF) ENVR Bits 31:4 Reserved, must be kept at reset value. Bit 3 VRR: Voltage reference buffer ready 0: the voltage reference buffer output is not ready. 1: the voltage reference buffer output reached the requested level. Bit 2 VRS: Voltage reference scale This bit selects the value generated by the voltage reference buffer.
Page 576: Table 108. Vrefbuf Register Map And Reset Values
Voltage reference buffer (VREFBUF) RM0351 18.3.3 VREFBUF register map The following table gives the VREFBUF register map and the reset values. Table 108. VREFBUF register map and reset values Offset Register VREFBUF_CSR 0x00 Reset value VREFBUF_CCR TRIM[5:0] 0x04 Reset value Refer to Section 2.2.2 on page 67 for the register boundary addresses.
Page 577: Comparator (Comp)
RM0351 Comparator (COMP) Comparator (COMP) 19.1 Introduction The device embeds two ultra-low power comparators COMP1, and COMP2 The comparators can be used for a variety of functions including: • Wake-up from low-power mode triggered by an analog signal, • Analog signal conditioning, •...
Page 578: Table 109. Comp1 Input Plus Assignment
Comparator (COMP) RM0351 19.3 COMP functional description 19.3.1 COMP block diagram The block diagram of the comparators is shown in Figure 138: Comparators block diagram. Figure 138. Comparators block diagram 19.3.2 COMP pins and internal signals The I/Os used as comparators inputs must be configured in analog mode in the GPIOs registers.
Page 579: Table 111. Comp2 Input Plus Assignment
RM0351 Comparator (COMP) Table 110. COMP1 input minus assignment (continued) COMP1_INM COMP1_INMSEL[2:0] ¾ V REFINT REFINT DAC Channel1 DAC Channel2 Table 111. COMP2 input plus assignment COMP2_INP COMP2_INPSEL Table 112. COMP2 input minus assignment COMP2_INM COMP2_INMSEL[2:0] ¼ V REFINT ½ V REFINT ¾...
Page 580: Figure 139. Window Mode
Comparator (COMP) RM0351 For this purpose, the comparator control and status registers can be write-protected (read- only). Once the programming is completed, the COMPxLOCK bit can be set to 1. This causes the whole register to become read-only, including the COMPxLOCK bit. The write protection can only be reset by a MCU reset.
Page 581: Figure 140. Comparator Hysteresis
RM0351 Comparator (COMP) Figure 140. Comparator hysteresis 19.3.7 Comparator output blanking function The purpose of the blanking function is to prevent the current regulation to trip upon short current spikes at the beginning of the PWM period (typically the recovery current in power switches anti parallel diodes).It consists of a selection of a blanking window which is a timer output compare signal.
Page 582: Table 113. Comparator Behavior In The Low Power Modes
Comparator (COMP) RM0351 19.3.8 COMP power and speed modes COMP1 and COMP2 power consumption versus propagation delay can be adjusted to have the optimum trade-off for a given application. The bits COMPx_PWR_MODE[1:0] in COMPx_CSR registers can be programmed as follows: 00: High speed / full power 01 or 10: Medium speed / medium power 11: Low speed / ultra-low-power...
Page 583: Table 114. Interrupt Control Bits
RM0351 Comparator (COMP) Table 114. Interrupt control bits Enable control Exit from Sleep Exit from Stop Exit from Interrupt event Event flag mode modes Standby mode VALUE in COMP1 output through EXTI COMP1_CSR VALUE in COMP2 output through EXTI COMP2_CSR DocID024597 Rev 3 583/1693...
Page 584: Comp Registers
Comparator (COMP) RM0351 19.6 COMP registers 19.6.1 Comparator 1 control and status register (COMP1_CSR) The COMP1_CSR is the Comparator 1 control/status register. It contains all the bits /flags related to comparator1. Address offset: 0x00 System reset value: 0x0000 0000 SCAL LOCK VALUE Res.
Page 585 RM0351 Comparator (COMP) Bits 20:18 BLANKING[2:0]: Comparator 1 blanking source selection bits These bits select which timer output controls the comparator 1 output blanking. 000: No blanking 001: TIM1 OC5 selected as blanking source 010: TIM2 OC3 selected as blanking source 100: TIM3 OC3 selected as blanking source All other values: reserved Bits 17:16 HYST[1:0]: Comparator 1 hysteresis selection bits...
Page 586: Comparator 2 Control And Status Register (Comp2_Csr)
Comparator (COMP) RM0351 19.6.2 Comparator 2 control and status register (COMP2_CSR) The COMP2_CSR is the Comparator 2 control/status register. It contains all the bits /flags related to comparator2. Address offset: 0x04 System reset value: 0x0000 0000 SCAL LOCK VALUE Res. Res.
Page 587 RM0351 Comparator (COMP) Bits 17:16 HYST[1:0]: Comparator 2 hysteresis selection bits These bits are set and cleared by software (only if LOCK not set). Select the Hysteresis voltage of the comparator 2. 00: No hysteresis 01: Low hysteresis 10: Medium hysteresis 11: High hysteresis Bit 15 POLARITY: Comparator 2 polarity selection bit This bit is set and cleared by software (only if LOCK not set).
Page 588: Table 115. Comp Register Map And Reset Values
Comparator (COMP) RM0351 19.6.3 COMP register map The following table summarizes the comparator registers. Table 115. COMP register map and reset values Offset Register COMP1_CSR 0x00 Reset value COMP2_CSR 0x04 Reset value Refer to Section 2.2.2 on page 67 for the register boundary addresses. 588/1693 DocID024597 Rev 3...
Page 589: Introduction
RM0351 Operational amplifiers (OPAMP) Operational amplifiers (OPAMP) 20.1 Introduction The device embeds two operational amplifiers with two inputs and one output each. The three I/Os can be connected to the external pins, this enables any type of external interconnections. The operational amplifier can be configured internally as a follower or as an amplifier with a non-inverting gain ranging from 2 to 16.
Page 590: Table 116. Operational Amplifier Possible Connections
Operational amplifiers (OPAMP) RM0351 20.3.2 Initial configuration The default configuration of the operational amplifier is a functional mode where the three IOs are connected to external pins. In the default mode the operational amplifier uses the factory trimming values. See electrical characteristics section of the datasheet for factory trimming conditions, usually the temperature is 30 °C and the voltage is 3 V.
Page 591: Figure 142. Standalone Mode: External Gain Setting Mode
RM0351 Operational amplifiers (OPAMP) 20.3.4 OPAMP modes The operational amplifier inputs and outputs are all accessible on terminals. The amplifiers can be used in multiple configuration environments: • Standalone mode (external gain setting mode) • Follower configuration mode • PGA modes Note: The amplifier output pin is directly connected to the output pad to minimize the output impedance.
Page 592: Figure 143. Follower Configuration
Operational amplifiers (OPAMP) RM0351 Follower configuration mode The procedure to use the OPAMP in follower mode is presented hereafter. • configure OPAMODE bits as “internal follower” • configure VP_SEL bits as “GPIO connected to VINP”. • As soon as the OPAEN bit is set, the signal on pin OPAMP_VINP is copied to pin OPAMP_VOUT.
Page 593: Figure 144. Pga Mode, Internal Gain Setting (X2/X4/X8/X16), Inverting Input Not Used
RM0351 Operational amplifiers (OPAMP) Programmable Gain Amplifier mode The procedure to use the OPAMP to amplify the amplitude of an input signal is presented hereafter. • configure OPAMODE bits as “internal PGA enabled”, • configure PGA_GAIN bits as “internal PGA Gain 2, 4, 8 or 16”, •...
Page 594: Figure 145. Pga Mode, Internal Gain Setting (X2/X4/X8/X16), Inverting Input Used For Filtering
Operational amplifiers (OPAMP) RM0351 Programmable Gain Amplifier mode with external filtering The procedure to use the OPAMP to amplify the amplitude of an input signal, with an external filtering, is presented hereafter. • configure OPAMODE bits as “internal PGA enabled”, •...
Page 595: Table 117. Operating Modes And Calibration
RM0351 Operational amplifiers (OPAMP) The user is able to switch from ‘factory’ values to ‘user’ trimmed values using the USERTRIM bit in the OPAMP_CSR register. This bit is reset at startup and so the ‘factory’ value are applied by default to the OPAMP trimming registers. User is liable to change the trimming values in calibration or in functional mode.
Page 596: Table 118. Effect Of Low-Power Modes On The Opamp
Operational amplifiers (OPAMP) RM0351 Calibration procedure Here are the steps to perform a full calibration of either one of the operational amplifiers: Select correct OPA_RANGE in OPAMP_CSR, then set the OPAEN bit in OPAMP_CSR to 1 to enable the operational amplifier. Set the USERTRIM bit in the OPAMP_CSR register to 1.
Page 597: Opamp Registers
RM0351 Operational amplifiers (OPAMP) Table 118. Effect of low-power modes on the OPAMP Mode Description Standby The OPAMP registers are powered down and must be re-initialized after exiting Standby or Shutdown mode. Shutdown 20.5 OPAMP registers 20.5.1 OPAMP1 control/status register (OPAMP1_CSR) Address offset: 0x00 Reset value: 0x0000 0000 OPA_...
Page 598: Opamp1 Offset Trimming Register In Normal Mode (Opamp1_Otr)
Operational amplifiers (OPAMP) RM0351 Bits 9:8 VM_SEL: Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. 00: GPIO connected to VINM (valid also in PGA mode for filtering) 01: Dedicated low leakage input, (available only on BGA132) connected to VINM (valid also in PGA mode for filtering) 1x: Inverting input not externally connected.
Page 599: Opamp2 Control/Status Register (Opamp2_Csr)
RM0351 Operational amplifiers (OPAMP) Reset value: 0x0000 XXXX (factory trimmed values) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TRIMLPOFFSETP Res. Res. Res. TRIMLPOFFSETN Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 TRIMLPOFFSETP[4:0]: Low-power mode trim for PMOS differential pairs Bits 7:5 Reserved, must be kept at reset value.
Page 600: Opamp2 Offset Trimming Register In Normal Mode (Opamp2_Otr)
Operational amplifiers (OPAMP) RM0351 Bits 9:8 VM_SEL: Inverting input selection These bits are used only when OPAMODE = 00, 01 or 10. 00: GPIO connected to VINM (valid also in PGA mode for filtering) 01: Dedicated low leakage input, (available only on BGA132) connected to VINM (valid also in PGA mode for filtering) 1x: Inverting input not externally connected.
Page 601 RM0351 Operational amplifiers (OPAMP) Reset value: 0x0000 XXXX (factory trimmed values) Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TRIMLPOFFSETP Res. Res. Res. TRIMLPOFFSETN Bits 31:13 Reserved, must be kept at reset value. Bits 12:8 TRIMLPOFFSETP[4:0]: Low-power mode trim for PMOS differential pairs Bits 7:5 Reserved, must be kept at reset value.
Page 602: Table 119. Opamp Register Map And Reset Values
Operational amplifiers (OPAMP) RM0351 20.5.7 OPAMP register map Table 119. OPAMP register map and reset values Offset Register OPAMP1_CSR 0x00 Reset value TRIM TRIM OPAMP1_OTR OFFSETP[4:0] OFFSETN[4:0] 0x04 Reset value OPAMP1_ TRIMLP TRIMLP LPOTR OFFSETP[4:0] OFFSETN[4:0] 0x08 Reset value OPAMP2_CSR 0x10 Reset value TRIM...
Page 603: Introduction
RM0351 Digital filter for sigma delta modulators (DFSDM) Digital filter for sigma delta modulators (DFSDM) 21.1 Introduction Digital filter for sigma delta modulators (DFSDM) is a high-performance module dedicated to interface external Σ∆ modulators to a microcontroller. It is featuring up to 8 external digital serial interfaces (channels) and up to 4 digital filters with flexible Sigma Delta stream digital processing options to offer up to 24-bit final ADC resolution.
Page 604: Dfsdm Main Features
Digital filter for sigma delta modulators (DFSDM) RM0351 21.2 DFSDM main features • Up to 8 multiplexed input digital serial channels: – configurable SPI interface to connect various Σ∆ modulators – configurable Manchester coded 1 wire interface support – maximum input clock frequency up to 20 MHz (10 MHz for Manchester coded stream) –...
Page 605: Figure 146. Single Dfsdm Block Diagram
RM0351 Digital filter for sigma delta modulators (DFSDM) 21.3 DFSDM functional description 21.3.1 DFSDM block diagram Figure 146. Single DFSDM block diagram DocID024597 Rev 3 605/1693...
Page 606: Table 120. Dfsdm External Pins
Digital filter for sigma delta modulators (DFSDM) RM0351 Note: This example shows 4 DFSDM interfaces and 8 input channels (max. configuration). 21.3.2 DFSDM pins and internal signals Table 120. DFSDM external pins Name Signal Type Remarks Power supply Digital power supply 1.65 - 3.6V. Power supply Digital ground power supply.
Page 607: Dfsdm Reset And Clocks
RM0351 Digital filter for sigma delta modulators (DFSDM) 21.3.3 DFSDM reset and clocks DFSDM on-off control The DFSDM interface is globally enabled by setting DFSDMEN=1 in the DFSDM_CHCFG0R1 register. Once DFSDM is globally enabled, all input channels (y=0..7) and digital filters DFSDMx (x=0..3) start to work if their enable bits are set (channel enable bit CHEN in DFSDM_CHCFGyR1 and DFSDMx enable bit DFEN in DFSDMx_CR1).
Page 608 Digital filter for sigma delta modulators (DFSDM) RM0351 Channel inputs selection Serial inputs (data and clock signals) from DFSDM_DATINy and DFSDM_CKINy pins can be redirected from the following channel. The serial input channel redirection is set by CHINSEL bit in DFSDM_CHCFGyR1 register. Channel redirection can be used to collect audio data from PDM (pulse density modulation) stereo microphone type.
Page 609 RM0351 Digital filter for sigma delta modulators (DFSDM) Internal clock sources - see SPICKSEL[1:0] in DFSDM_CHCFGyR1 register: • DFSDM_CKOUT signal: – For connection to external Σ∆ modulator which uses directly its clock input (from DFSDM_CKOUT) to generate its output serial communication clock. –...
Page 610: Figure 147. Channel Transceiver Timing Diagrams
Digital filter for sigma delta modulators (DFSDM) RM0351 Figure 147. Channel transceiver timing diagrams 610/1693 DocID024597 Rev 3...
Page 611: Figure 148. Clock Absence Timing Diagram For Spi
RM0351 Digital filter for sigma delta modulators (DFSDM) Clock absence detection Channels serial clock inputs can be checked for clock absence/presence to ensure the correct operation of conversion and error reporting. Clock absence detection can be enabled or disabled on each input channel y by bit CKABEN in DFSDMx_CHCFGyR1 register.
Page 612 Digital filter for sigma delta modulators (DFSDM) RM0351 If Manchester data format is used, then the clock absence means that the clock recovery is unable to perform from Manchester coded signal. For a correct clock recovery, it is first necessary to receive data with 1 to 0 or 0 to 1 transition (see Figure 150 for Manchester synchronization).
Page 613: Figure 149. Clock Absence Timing Diagram For Manchester Coding
RM0351 Digital filter for sigma delta modulators (DFSDM) Figure 149. Clock absence timing diagram for Manchester coding Manchester/SPI code synchronization The Manchester coded stream must be synchronized the first time after enabling the channel (CHEN=1 in DFSDM_CHCFGyR1 register). The synchronization ends when a data transition from 0 to 1 or from 1 to 0 (to be able to detect valid data edge) is received.
Page 614: Figure 150. First Conversion For Manchester Coding (Manchester Synchronization)
Digital filter for sigma delta modulators (DFSDM) RM0351 SPI coded stream is synchronized after first detection of clock input signal (valid rising/falling edge). Note: When the transceiver is not yet synchronized, the clock absence flag is set and cannot be cleared by CLRCKABF[y] bit (in DFSDMx_ICR register).
Page 615 RM0351 Digital filter for sigma delta modulators (DFSDM) bypassed (FOSR=0, only integrator is active, CNVCNT[27:0]=0 in DFSDMx_CNVTIMR register). In case of parallel data input (Section 21.3.6: Parallel data inputs) the measured frequency is the average input data rate during one conversion. Note: When conversion is interrupted (e.g.
Page 616: Configuring The Input Serial Interface
Digital filter for sigma delta modulators (DFSDM) RM0351 21.3.5 Configuring the input serial interface The following parameters must be configured for the input serial interface: • Output clock predivider. There is a programmable predivider to generate the output clock from DFSDM clock (2 - 256). It is defined in DFSDMx_CR1 register. •...
Page 617 RM0351 Digital filter for sigma delta modulators (DFSDM) address is the address of DFSDM_CHDATINyR register. Data are transferred at DMA transfer speed from memory to DFSDM parallel input. This DMA transfer is different from DMA used to read DFSDM conversion results. Both DMA can be used at the same time - first DMA (configured as memory-to-memory transfer) for input data writings and second DMA (configured as peripheral-to-memory transfer) for data results reading.
Page 618: Figure 151. Dfsdm_Chdatinyr Registers Operation Modes And Assignment
Digital filter for sigma delta modulators (DFSDM) RM0351 Figure 151. DFSDM_CHDATINyR registers operation modes and assignment The write into DFSDM_CHDATINyR register to load one or two samples must be performed after the selected input channel (channel y) is enabled for data collection (starting conversion for channel y).
Page 619: Figure 152. Example: Sinc3 Filter Response
RM0351 Digital filter for sigma delta modulators (DFSDM) 21.3.8 Digital filter configuration DFSDM contains a Sinc type digital filter implementation. This Sinc filter performs an input digital data stream filtering, which results in decreasing the output data rate (decimation) and increasing the output data resolution. The Sinc digital filter is configurable in order to reach the required output data rates and required output data resolution.
Page 620: Table 123. Filter Maximum Output Resolution (Peak Data Values From Filter Output)
Digital filter for sigma delta modulators (DFSDM) RM0351 Table 123. Filter maximum output resolution (peak data values from filter output) for some FOSR values FOSR Sinc Sinc FastSinc Sinc Sinc Sinc +/- x +/- x +/- 2x +/- x +/- x +/- x +/- 4 +/- 16...
Page 621 RM0351 Digital filter for sigma delta modulators (DFSDM) Analog watchdog conversions on input channels are independent from standard conversions. In this case, the analog watchdog uses its own filters and signal processing on each input channel independently from the main injected or regular conversions. Analog watchdog conversions are performed in a continuous mode on the selected input channels in order to watch channels also when main injected or regular conversions are paused (RCIP = 0, JCIP = 0).
Page 622: Short-Circuit Detector
Digital filter for sigma delta modulators (DFSDM) RM0351 cannot be used for analog watchdog feature at this input clock speed. Therefore user must properly configure the number of watched channels and analog watchdog filter parameters with respect to input sampling clock speed and DFSDM frequency. Analog watchdog filter data for given channel y is available for reading by firmware on field WDATA[15:0] in DFSDM_CHWDATyR register.
Page 623: Extremes Detector
RM0351 Digital filter for sigma delta modulators (DFSDM) There is an upcounting counter on each input channel which is counting consecutive 0’s or 1’s on serial data receiver outputs. A counter is restarted if there is a change in the data stream received - 1 to 0 or 0 to 1 change of data signal.
Page 624: Signed Data Format
Digital filter for sigma delta modulators (DFSDM) RM0351 DFSDM_CKIN ⁄ ---------------------------------------------------------------------------------- - Datarate samples ...FAST = 0, FastSinc filter ⋅ – DFSDM_CKIN ⁄ ---------------------------------- - Datarate samples ...FAST = 1 ⋅ Maximum output data rate in case of parallel data input: DATAIN_RATE ⁄...
Page 625: Launching Conversions
RM0351 Digital filter for sigma delta modulators (DFSDM) A Σ∆ modulator output is always assumed in a signed format (a data stream of zeros and ones from a Σ∆ modulator represents values -1 and +1). Signed data format in registers: Data is in a signed format in registers for final output data, analog watchdog, extremes detector, offset correction.
Page 626: Request Precedence
Digital filter for sigma delta modulators (DFSDM) RM0351 The regular conversions executing in continuous mode can be stopped by writing ‘0’ to RCONT. After clearing RCONT, the on-going conversion is stopped immediately. In continuous mode, the data rate can be increased by setting the FAST bit in the DFSDMx_CR1 register.
Page 627: Power Optimization In Run Mode
RM0351 Digital filter for sigma delta modulators (DFSDM) the sequence of injected conversions finishes, the continuous regular conversions start again if RCONT is still set (and RPEND bit will signalize the delayed start on the first regular conversion result). Precedence also matters when actions are initiated by the same write to DFSDM, or if multiple actions are pending at the end of another action.
Page 628: Table 125. Dfsdm Interrupt Requests
Digital filter for sigma delta modulators (DFSDM) RM0351 – occurred when converted data (output data or data from analog watchdog filter - according to AWFSEL bit setting in DFSDMx_CR1 register) crosses over/under high/low thresholds in DFSDMx_AWHTR / DFSDMx_AWLTR registers – enabled by AWDIE bit in DFSDMx_CR2 register (on selected channels AWDCH[7:0]) –...
Page 629: Dfsdm Dma Transfer
RM0351 Digital filter for sigma delta modulators (DFSDM) 21.5 DFSDM DMA transfer To decrease the CPU intervention, conversions can be transferred into memory using a DMA transfer. A DMA transfer for injected conversions is enabled by setting bit JDMAEN=1 in DFSDMx_CR1 register. A DMA transfer for regular conversions is enabled by setting bit RDMAEN=1 in DFSDMx_CR1 register.
Page 630 Digital filter for sigma delta modulators (DFSDM) RM0351 Bits 23:16 CKOUTDIV[7:0]: Output serial clock divider 0: Output clock generation is disabled (DFSDM_CKOUT signal is set to low state) 1- 255: Defines the division of system clock for the serial clock output for DFSDM_CKOUT signal in range 2 - 256 (Divider = CKOUTDIV+1).
Page 631 RM0351 Digital filter for sigma delta modulators (DFSDM) Bit 5 SCDEN: Short-circuit detector enable on channel y 0: Input channel y will not be guarded by the short-circuit detector 1: Input channel y will be continuously guarded by the short-circuit detector Bit 4 Reserved, must be kept at reset value.
Page 632: Dfsdm_Awscdyr) (Y=0..7)
Digital filter for sigma delta modulators (DFSDM) RM0351 Bits 31:8 OFFSET[23:0]: 24-bit calibration offset for channel y For channel y, OFFSET is applied to the results of each conversion from this channel. This value is set by software. Bits 7:3 DTRBS[4:0]: Data right bit-shift for channel y 0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right will be performed to have final results.
Page 633 RM0351 Digital filter for sigma delta modulators (DFSDM) Bits 15:12 BKSCD[3:0]: Break signal assignment for short-circuit detector on channel y BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y Bits 11:8 Reserved, must be kept at reset value.
Page 634: Dfsdmx Module Registers (X=0..3)
Digital filter for sigma delta modulators (DFSDM) RM0351 Bits 31:16 INDAT0[15:0]: Input data for channel y or channel y+1 Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2. Data can be written by CPU/DMA (if DATMPX[1:0]=2). If DATPACK[1:0]=0 (standard mode) INDAT0[15:0] is write protected (not used for input sample).
Page 635 RM0351 Digital filter for sigma delta modulators (DFSDM) Bit 31 Reserved, must be kept at reset value. Bit 30 AWFSEL: Analog watchdog fast mode select 0: Analog watchdog on data output value (after the digital filter). The comparison is done after offset correction and shift 1: Analog watchdog on channel transceivers value (after watchdog filter) Bit 29 FAST: Fast conversion mode selection for regular conversions...
Page 636 Digital filter for sigma delta modulators (DFSDM) RM0351 Bit 17 RSWSTART: Software start of a conversion on the regular channel 0: Writing ‘0’ has no effect 1: Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to become ‘1’.
Page 637: Dfsdm Control Register 2 (Dfsdmx_Cr2)
RM0351 Digital filter for sigma delta modulators (DFSDM) Bit 2 Reserved, must be kept at reset value. Bit 1 JSWSTART: Start a conversion of the injected group of channels 0: Writing ‘0’ has no effect. 1: Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing JCIP to become ‘1’...
Page 638: Dfsdm Interrupt And Status Register (Dfsdmx_Isr)
Digital filter for sigma delta modulators (DFSDM) RM0351 Bit 5 SCDIE: Short-circuit detector interrupt enable 0: short-circuit detector interrupt is disabled 1: short-circuit detector interrupt is enabled Please see the explanation of SCDF[7:0] in DFSDMx_ISR. Note: SCDIE is present only in DFSDM0_CR2 register (filter x=0) Bit 4 AWDIE: Analog watchdog interrupt enable 0: Analog watchdog interrupt is disabled 1: Analog watchdog interrupt is enabled...
Page 639 RM0351 Digital filter for sigma delta modulators (DFSDM) Bits 31:24 SCDF[7:0]: short-circuit detector flag SDCF[y]=0: No short-circuit detector event occurred on channel y SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the DFSDM_AWSCDyR registers This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in the DFSDMx_ICR register.
Page 640: Dfsdm Interrupt Flag Clear Register (Dfsdmx_Icr)
Digital filter for sigma delta modulators (DFSDM) RM0351 Bit 2 JOVRF: Injected conversion overrun flag 0: No injected conversion overrun has occurred 1: An injected conversion overrun has occurred, which means that an injected conversion finished while JEOCF was already ‘1’. JDATAR is not affected by overruns This bit is set by hardware.
Page 641: Dfsdm Filter Control Register (Dfsdmx_Fcr)
RM0351 Digital filter for sigma delta modulators (DFSDM) Bit 3 CLRROVRF: Clear the regular conversion overrun flag 0: Writing ‘0’ has no effect 1: Writing ‘1’ clears the ROVRF bit in the DFSDMx_ISR register Bit 2 CLRJOVRF: Clear the injected conversion overrun flag 0: Writing ‘0’...
Page 642: Dfsdm Data Register For Injected Group (Dfsdmx_Jdatar)
Digital filter for sigma delta modulators (DFSDM) RM0351 Bits 31:29 FORD[2:0]: Sinc filter order 0: FastSinc filter type 1: Sinc filter type 2: Sinc filter type 3: Sinc filter type 4: Sinc filter type 5: Sinc filter type 6-7: Reserved FOSR ⎛...
Page 643: Dfsdm Data Register For The Regular Channel (Dfsdmx_Rdatar)
RM0351 Digital filter for sigma delta modulators (DFSDM) Bits 31:8 JDATA[23:0]: Injected group conversion data When each conversion of a channel in the injected group finishes, its resulting data is stored in this field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF. Bits 7:3 Reserved, must be kept at reset value.
Page 644: Dfsdm Analog Watchdog Low Threshold Register (Dfsdmx_Awltr)
Digital filter for sigma delta modulators (DFSDM) RM0351 21.7.9 DFSDM analog watchdog high threshold register (DFSDMx_AWHTR) Address offset: 0x100 * (x+1) + 0x020, x = 0...3 Reset value: 0x0000 0000 AWHT[23:8] AWHT[7:0] Res. Res. Res. Res. BKAWH[3:0] Bits 31:8 AWHT[23:0]: Analog watchdog high threshold These bits are written by software to define the high threshold for the analog watchdog.
Page 645: Dfsdm Analog Watchdog Status Register (Dfsdmx_Awsr)
RM0351 Digital filter for sigma delta modulators (DFSDM) Bits 31:8 AWLT[23:0]: Analog watchdog low threshold These bits are written by software to define the low threshold for the analog watchdog. Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define the 16-bit threshold as compared with the analog watchdog filter output (because data coming from the analog watchdog filter are up to a 16-bit resolution).
Page 646: Dfsdm Extremes Detector Maximum Register (Dfsdmx_Exmax)
Digital filter for sigma delta modulators (DFSDM) RM0351 Bits 31:16 Reserved, must be kept at reset value. Bits 15:8 CLRAWHTF[7:0]: Clear the analog watchdog high threshold flag CLRAWHTF[y]=0: Writing ‘0’ has no effect CLRAWHTF[y]=1: Writing ‘1’ to position y clears the corresponding AWHTF[y] bit in the DFSDMx_AWSR register Bits 7:0 CLRAWLTF[7:0]: Clear the analog watchdog low threshold flag CLRAWLTF[y]=0: Writing ‘0’...
Page 647: Dfsdm Conversion Timer Register (Dfsdmx_Cnvtimr)
RM0351 Digital filter for sigma delta modulators (DFSDM) Bits 31:8 EXMIN[23:0]: Extremes detector minimum value These bits are set by hardware and indicate the lowest value converted by DFSDM. EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register. Bits 7:3 Reserved, must be kept at reset value.
Page 648: Table 126. Dfsdm Register Map And Reset Values
Digital filter for sigma delta modulators (DFSDM) RM0351 21.8 DFSDM register map The following table summarizes the DFSDM registers. Table 126. DFSDM register map and reset values Offset Register DFSDM_ CKOUTDIV[7:0] CHCFG0R1 0x00 reset value DFSDM_ OFFSET[23:0] DTRBS[4:0] CHCFG0R2 0x04 reset value DFSDM_ AWFOSR[4:0]...
Page 649 RM0351 Digital filter for sigma delta modulators (DFSDM) Table 126. DFSDM register map and reset values (continued) Offset Register DFSDM_ CHCFG2R1 0x40 reset value DFSDM_ OFFSET[23:0] DTRBS[4:0] CHCFG2R2 0x44 reset value DFSDM_ AWFOSR[4:0] BKSCD[3:0] SCDT[7:0] AWSCD2R 0x48 reset value DFSDM_ WDATA[15:0] CHWDAT2R 0x4C...
Page 650 Digital filter for sigma delta modulators (DFSDM) RM0351 Table 126. DFSDM register map and reset values (continued) Offset Register DFSDM_ OFFSET[23:0] DTRBS[4:0] CHCFG4R2 0x84 reset value DFSDM_ AWFOSR[4:0] BKSCD[3:0] SCDT[7:0] AWSCD4R 0x88 reset value DFSDM_ WDATA[15:0] CHWDAT4R 0x8C reset value DFSDM_ INDAT1[15:0] INDAT0[15:0]...
Page 651 RM0351 Digital filter for sigma delta modulators (DFSDM) Table 126. DFSDM register map and reset values (continued) Offset Register DFSDM_ AWFOSR[4:0] BKSCD[3:0] SCDT[7:0] AWSCD6R 0xC8 reset value DFSDM_ WDATA[15:0] CHWDAT6R 0xCC reset value DFSDM_ INDAT1[15:0] INDAT0[15:0] CHDATIN6R 0xD0 reset value 0xD4 - Reserved 0xDC...
Page 652: Table 127. Dfsdmx Register Map And Reset Values
Digital filter for sigma delta modulators (DFSDM) RM0351 The following table summarizes the DFSDMx registers. Table 127. DFSDMx register map and reset values Offset Register DFSDM0_ RCH[2:0] 0x100 reset value DFSDM0_ AWDCH[7:0] EXCH[7:0] 0x104 reset value DFSDM0_ SCDF[7:0] CKABF[7:0] 0x108 reset value DFSDM0_ CLRSCDF[7:0]...
Page 653 RM0351 Digital filter for sigma delta modulators (DFSDM) Table 127. DFSDMx register map and reset values (continued) Offset Register DFSDM0_ EXMAX[23:0] EXMAX 0x130 reset value DFSDM0_ EXMIN[23:0] EXMIN 0x134 reset value DFSDM0_ CNVCNT[27:0] CNVTIMR 0x138 reset value 0x13C - Reserved 0x1FC DFSDM1_ RCH[2:0]...
Page 654 Digital filter for sigma delta modulators (DFSDM) RM0351 Table 127. DFSDMx register map and reset values (continued) Offset Register DFSDM1_ RDATA RDATA[23:0] RDATAR CH[2:0] 0x21C reset value DFSDM1_ AWHT[23:0] BKAWH[3:0] AWHTR 0x220 reset value DFSDM1_ AWLT[23:0] BKAWL[3:0] AWLTR 0x224 reset value DFSDM1_ AWHTF[7:0] AWLTF[7:0]...
Page 655 RM0351 Digital filter for sigma delta modulators (DFSDM) Table 127. DFSDMx register map and reset values (continued) Offset Register DFSDM2_ JCHG[7:0] JCHGR 0x310 reset value DFSDM2_ FOSR[9:0] IOSR[7:0] 0x314 reset value DFSDM2_ JDATA[23:0] JDATAR 0x318 reset value DFSDM2_ RDATA RDATA[23:0] RDATAR CH[2:0] 0x31C...
Page 656 Digital filter for sigma delta modulators (DFSDM) RM0351 Table 127. DFSDMx register map and reset values (continued) Offset Register DFSDM3_ AWDCH[7:0] EXCH[7:0] 0x404 reset value DFSDM3_ 0x408 reset value DFSDM3_ 0x40C reset value JCHG[7:0] DFSDM3_ JCHGR 0x410 reset value DFSDM3_ FOSR[9:0] IOSR[7:0] 0x414...
Page 657 RM0351 Digital filter for sigma delta modulators (DFSDM) Table 127. DFSDMx register map and reset values (continued) Offset Register DFSDM3_ EXMIN[23:0] EXMIN 0x434 reset value DFSDM3_ CNVCNT[27:0] CNVTIMR 0x438 reset value 0x43C - Reserved 0x4FC Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses.
Page 658: Liquid Crystal Display Controller (Lcd)
Liquid crystal display controller (LCD) RM0351 Liquid crystal display controller (LCD) 22.1 Introduction The LCD controller is a digital controller/driver for monochrome passive liquid crystal display (LCD) with up to 8 common terminals and up to 44 segment terminals to drive 176 (44x4) or 320 (40x8) LCD picture elements (pixels).
Page 659: Lcd Main Features
RM0351 Liquid crystal display controller (LCD) 22.2 LCD main features • Highly flexible frame rate control. • Supports Static, 1/2, 1/3, 1/4 and 1/8 duty. • Supports Static, 1/2, 1/3 and 1/4 bias. • Double buffered memory allows data in LCD_RAM registers to be updated at any time by the application firmware without affecting the integrity of the data displayed.
Page 660: Figure 153. Lcd Controller Block Diagram
Liquid crystal display controller (LCD) RM0351 22.3 LCD functional description 22.3.1 General description The LCD controller has five main blocks (see Figure 153): Figure 153. LCD controller block diagram Note: LCDCLK is the same as RTCCLK. Please refer to the RTC/LCD clock description in the RCC section of this manual.
Page 661: Table 128. Example Of Frame Rate Calculation
RM0351 Liquid crystal display controller (LCD) 22.3.2 Frequency generator This clock source must be stable in order to obtain accurate LCD timing and hence minimize DC voltage offset across LCD segments. The input clock LCDCLK can be divided by any value from 1 to 2 x 31 (see Section 22.6.2: LCD frame control register (LCD_FCR) on page...
Page 662: Figure 154. 1/3 Bias, 1/4 Duty
Liquid crystal display controller (LCD) RM0351 addition, a dedicated blink prescaler selects the blink frequency. This frequency is defined (BLINKF + 3) BLINK ck_div with BLINKF[2:0] = 0, 1, 2, ... ,7 The blink frequency achieved is in the range of 0.5 Hz, 1 Hz, 2 Hz or 4 Hz. 22.3.3 Common driver Common signals are generated by the common driver block (see...
Page 663: Figure 155. Static Duty Case 1
RM0351 Liquid crystal display controller (LCD) COM[n] n[0 to 7] is active during phase n in the odd frame, so the COM pin is driven to During phase n of the even frame the COM pin is driven to V In the case of 1/3 or 1/4) bias: •...
Page 664: Figure 156. Static Duty Case 2
Liquid crystal display controller (LCD) RM0351 Figure 156. Static duty case 2 In this mode, the segment terminals are multiplexed and each of them control four pixels. A pixel is activated only when both of its corresponding SEG and COM lines are active in the same phase.
Page 665: Figure 157. 1/2 Duty, 1/2 Bias
RM0351 Liquid crystal display controller (LCD) Figure 157. 1/2 duty, 1/2 bias 22.3.4 Segment driver The segment driver block controls the SEG lines according to the pixel data coming from the 8 to 1 mux driven in each phase by the common driver block. In the case of 1/4 or 1/8 duty When COM[0] is active, the pixel information (active/inactive) related to the pixel connected to COM[0] (content of the first two LCD_RAM locations) goes through the 8 to 1 mux.
Page 666: Figure 158. 1/3 Duty, 1/3 Bias
Liquid crystal display controller (LCD) RM0351 Figure 158. 1/3 duty, 1/3 bias 666/1693 DocID024597 Rev 3...
Page 667: Figure 159. 1/4 Duty, 1/3 Bias
RM0351 Liquid crystal display controller (LCD) Figure 159. 1/4 duty, 1/3 bias DocID024597 Rev 3 667/1693...
Page 668: Figure 160. 1/8 Duty, 1/4 Bias
Liquid crystal display controller (LCD) RM0351 Figure 160. 1/8 duty, 1/4 bias 668/1693 DocID024597 Rev 3...
Page 669: Table 129. Blink Frequency
RM0351 Liquid crystal display controller (LCD) Blink The segment driver also implements a programmable blink feature to allow some pixels to continuously switch on at a specific frequency. The blink mode can be configured by the BLINK[1:0] bits in the LCD_FCR register, making possible to blink up to 1, 2, 4, 8 or all pixels (see Section 22.6.2: LCD frame control register (LCD_FCR)).
Page 670 Liquid crystal display controller (LCD) RM0351 In case the internal step-up converter is used (capacitor C on VLCD pin is required): • Configure the VLCD pin as alternate function LCD in the GPIO_AFR register. • Wait for the external capacitor C to be charged (C connected to the VLCD pin, approximately 2 ms for C...
Page 671: Figure 161. Vlcd Pin For 1/2 1/3 1/4 Bias
RM0351 Liquid crystal display controller (LCD) Figure 161. VLCD pin for 1/2 1/3 1/4 bias 1. R : Low value resistor network. R : High value resistor network. The R divider can be always switched on using the HD bit in the LCD_FCR configuration register (see Section 22.6.2).
Page 672: Figure 162. Deadtime
Liquid crystal display controller (LCD) RM0351 In buffer mode, intermediate voltages are generated by the high value resistor bridge R reduce power consumption, the low value resistor bridge R is automatically disabled whatever the HD bit or PON bits configuration. Buffers can be used independently of the V supply source (internal or external) but can only be enabled or disabled when LCD controller is not activated.
Page 673: Double Buffer Memory
RM0351 Liquid crystal display controller (LCD) 22.3.6 Double buffer memory Using its double buffer memory the LCD controller ensures the coherency of the displayed information without having to use interrupts to control LCD_RAM modification. The application software can access the first buffer level (LCD_RAM) through the APB interface.
Page 674: Table 130. Remapping Capability
Liquid crystal display controller (LCD) RM0351 Summary of COM and SEG functions versus duty and remap All the possible ways of multiplexing the COM and SEG functions are described in Table 130. Figure 163 gives examples showing the signal connections to the external pins. Table 130.
Page 675 RM0351 Liquid crystal display controller (LCD) Table 130. Remapping capability (continued) Configuration bits LQFP144 CSP72 BGA132/ Output pin Function LQFP64 DUTY MUX_SEG LQFP100 COM3 not used COM[2:0] COM[2:0] 44x3 SEG[43:40]/SEG[31:28]/COM[7:4] SEG[43:40] SEG[39:0] SEG[39:0] COM3 not used COM[2:0] COM[2:0] SEG[43:40]/SEG[31:28]/COM[7:4] SEG[31:28] 40x3 SEG[39:32] SEG[39:32]...
Page 676 Liquid crystal display controller (LCD) RM0351 Table 130. Remapping capability (continued) Configuration bits LQFP144 CSP72 BGA132/ Output pin Function LQFP64 DUTY MUX_SEG LQFP100 COM[3:2] not used COM[1:0] COM[1:0] 28x2 SEG[43:40]/SEG[31:28]/COM[7:4] not used SEG[27:0] SEG[27:0] COM[3:2] not used COM[1:0] COM[1:0] 32x2 SEG[43:40]/SEG[31:28]/COM[7:4] SEG[31:28] SEG[27:0]...
Page 677: Figure 163. Seg/Com Mux Feature Example
RM0351 Liquid crystal display controller (LCD) Figure 163. SEG/COM mux feature example DocID024597 Rev 3 677/1693...
Page 678: Figure 164. Flowchart Example
Liquid crystal display controller (LCD) RM0351 22.3.8 Flowchart Figure 164. Flowchart example 678/1693 DocID024597 Rev 3...
Page 679: Table 131. Lcd Behavior In Low-Power Modes
(LCD global interrupt), or be grouped into 2 interrupt vectors (LCD SOF interrupt and LCD UDD interrupt). Refer to the Table 42: STM32L4x6 vector table details. In order to enable the LCD interrupts, the following sequence is required:...
Page 680 Liquid crystal display controller (LCD) RM0351 Configure and enable the LCD IRQ channel in the NVIC Configure the LCD to generate interrupts 680/1693 DocID024597 Rev 3...
Page 681: Lcd Registers
RM0351 Liquid crystal display controller (LCD) 22.6 LCD registers The peripheral registers have to be accessed by words (32-bit). 22.6.1 LCD control register (LCD_CR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 682: Lcd Frame Control Register (Lcd_Fcr)
Liquid crystal display controller (LCD) RM0351 Bits 4:2 DUTY[2:0]: Duty selection These bits determine the duty cycle. Values 101, 110 and 111 are forbidden. 000: Static duty 001: 1/2 duty 010: 1/3 duty 011: 1/4 duty 100: 1/8 duty 101: Reserved 110: Reserved 111: Reserved Bit 1 VSEL: Voltage source selection...
Page 683 RM0351 Liquid crystal display controller (LCD) Bits 31:26 Reserved, must be kept at reset value Bits 25:22 PS[3:0]: PS 16-bit prescaler These bits are written by software to define the division factor of the PS 16-bit prescaler. ck_ps = LCDCLK/(2). See Section 22.3.2.
Page 684 Liquid crystal display controller (LCD) RM0351 Bits 9:7 DEAD[2:0]: Dead time duration These bits are written by software to configure the length of the dead time between frames. During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast without modifying the frame rate.
Page 685 RM0351 Liquid crystal display controller (LCD) Note: The data in this register can be updated any time, however the new values are applied only at the beginning of the next frame (except for UDDIE, SOFIE that affect the device behavior immediately).
Page 686: Lcd Status Register (Lcd_Sr)
Liquid crystal display controller (LCD) RM0351 22.6.3 LCD status register (LCD_SR) Address offset: 0x08 Reset value: 0x0000 0020 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 687 RM0351 Liquid crystal display controller (LCD) Bit 2 UDR: Update display request Each time software modifies the LCD_RAM it must set the UDR bit to transfer the updated data to the second level buffer. The UDR bit stays set until the end of the update and during this time the LCD_RAM is write protected.
Page 688: Lcd Clear Register (Lcd_Clr)
Liquid crystal display controller (LCD) RM0351 22.6.4 LCD clear register (LCD_CLR) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 689: Table 133. Lcd Register Map And Reset Values
RM0351 Liquid crystal display controller (LCD) 22.6.6 LCD register map The following table summarizes the LCD registers. Table 133. LCD register map and reset values Register DUTY LCD_CR [2:0] 0x00 Reset value 0 0 0 0 0 0 0 0 DEAD PS[3:0] DIV[3:0]...
Page 690 Liquid crystal display controller (LCD) RM0351 Table 133. LCD register map and reset values (continued) Register 0x2C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCD_RAM (COM3) 0x30...
Page 691: Touch Sensing Controller (Tsc)
RM0351 Touch sensing controller (TSC) Touch sensing controller (TSC) 23.1 Introduction The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application. Capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (for example glass, plastic).
Page 692: Figure 165. Tsc Block Diagram
Touch sensing controller (TSC) RM0351 23.3 TSC functional description 23.3.1 TSC block diagram The block diagram of the touch sensing controller is shown in Figure 165: TSC block diagram. Figure 165. TSC block diagram 23.3.2 Surface charge transfer acquisition overview The surface charge transfer acquisition is a proven, robust and efficient way to measure a capacitance.
Page 693: Figure 166. Surface Charge Transfer Analog I/O Group Structure
RM0351 Touch sensing controller (TSC) The remaining GPIOs are dedicated to the electrodes and are commonly called channels. For some specific needs (such as proximity detection), it is possible to simultaneously enable more than one channel per analog I/O group. Figure 166.
Page 694: Table 134. Acquisition Sequence Summary
Touch sensing controller (TSC) RM0351 Table 134. Acquisition sequence summary G1_IO1 G1_IO2 G1_IO3 G1_IO4 State State description (electrode) (sampling) (electrode) (electrode) Output open- Input floating drain low with Input floating with analog switch Discharge all C with analog analog switch closed switch closed closed...
Page 695: Figure 168. Charge Transfer Acquisition Sequence
RM0351 Touch sensing controller (TSC) 23.3.4 Charge transfer acquisition sequence An example of a charge transfer acquisition sequence is detailed in Figure 168. Figure 168. Charge transfer acquisition sequence For higher flexibility, the charge transfer frequency is fully configurable. Both the pulse high state (charge of C ) and the pulse low state (transfer of charge from C to C...
Page 696: Table 135. Spread Spectrum Deviation Versus Ahb Clock Frequency
Touch sensing controller (TSC) RM0351 23.3.5 Spread spectrum feature The spread spectrum feature allows to generate a variation of the charge transfer frequency. This is done to improve the robustness of the charge transfer acquisition in noisy environments and also to reduce the induced emission. The maximum frequency variation is in the range of 10% to 50% of the nominal charge transfer period.
Page 697: Table 136. I/O State Depending On Its Mode And Iodef Bit Value
RM0351 Touch sensing controller (TSC) 23.3.7 Sampling capacitor I/O and channel I/O mode selection To allow the GPIOs to be controlled by the touch sensing controller, the corresponding alternate function must be enabled through the standard GPIO registers and the GPIOxAFR registers.
Page 698: Acquisition Mode
Touch sensing controller (TSC) RM0351 Note: During the acquisition phase and even if the TSC peripheral alternate function is not enabled, as soon as the TSC_IOSCR or TSC_IOCCR bit is set, the corresponding GPIO analog switch is automatically controlled by the touch sensing controller. 23.3.8 Acquisition mode The touch sensing controller offers two acquisition modes:...
Page 699: Table 137. Effect Of Low-Power Modes On Tsc
RM0351 Touch sensing controller (TSC) 23.4 TSC low-power modes Table 137. Effect of low-power modes on TSC Mode Description Sleep No effect. Peripheral interrupts cause the device to exit Sleep mode. Low power run No effect. Low power sleep No effect. Peripheral interrupts cause the device to exit Low-power sleep mode. Stop 0 / Stop 1 Peripheral registers content is kept.
Page 700: Tsc Registers
Touch sensing controller (TSC) RM0351 23.6 TSC registers Refer to Section 1.1 on page 61 of the reference manual for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by words (32-bit). 23.6.1 TSC control register (TSC_CR) Address offset: 0x00 Reset value: 0x0000 0000 CTPH[3:0]...
Page 701 RM0351 Touch sensing controller (TSC) Bit 16 SSE: Spread spectrum enable This bit is set and cleared by software to enable/disable the spread spectrum feature. 0: Spread spectrum disabled 1: Spread spectrum enabled Note: This bit must not be modified when an acquisition is ongoing. Bit 15 SSPSC: Spread spectrum prescaler This bit is set and cleared by software.
Page 702: Tsc Interrupt Enable Register (Tsc_Ier)
Touch sensing controller (TSC) RM0351 Bit 2 AM: Acquisition mode This bit is set and cleared by software to select the acquisition mode. 0: Normal acquisition mode (acquisition starts as soon as START bit is set) 1: Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) Note: This bit must not be modified when an acquisition is ongoing.
Page 703: Tsc Interrupt Clear Register (Tsc_Icr)
RM0351 Touch sensing controller (TSC) 23.6.3 TSC interrupt clear register (TSC_ICR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 704: Tsc Interrupt Status Register (Tsc_Isr)
Touch sensing controller (TSC) RM0351 23.6.4 TSC interrupt status register (TSC_ISR) Address offset: 0x0C Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 705: Tsc I/O Analog Switch Control Register (Tsc_Ioascr)
RM0351 Touch sensing controller (TSC) 23.6.6 TSC I/O analog switch control register (TSC_IOASCR) Address offset: 0x18 Reset value: 0x0000 0000 G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 Bits 31:0 Gx_IOy: Gx_IOy analog switch enable These bits are set and cleared by software to enable/disable the Gx_IOy analog switch.
Page 706: Tsc I/O Channel Control Register (Tsc_Ioccrtsc_Ioccr)
Touch sensing controller (TSC) RM0351 23.6.8 TSC I/O channel control register (TSC_IOCCRTSC_IOCCR) Address offset: 0x28 Reset value: 0x0000 0000 G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1 G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1 Bits 31:0 Gx_IOy: Gx_IOy channel mode These bits are set and cleared by software to configure the Gx_IOy as a channel I/O.
Page 707: Table 139. Tsc Register Map And Reset Values
RM0351 Touch sensing controller (TSC) Bits 23:16 GxS: Analog I/O group x status These bits are set by hardware when the acquisition on the corresponding enabled analog I/O group x is complete. They are cleared by hardware when a new acquisition is started. 0: Acquisition on analog I/O group x is ongoing or not started 1: Acquisition on analog I/O group x is complete Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O...
Page 708 Touch sensing controller (TSC) RM0351 Table 139. TSC register map and reset values (continued) Offset Register TSC_ICR 0x0008 Reset value TSC_ISR 0x000C Reset value TSC_IOHCR 0x0010 Reset value 0x0014 Reserved TSC_IOASCR 0x0018 Reset value 0x001C Reserved TSC_IOSCR 0x0020 Reset value 0x0024 Reserved TSC_IOCCR...
Page 709 RM0351 Touch sensing controller (TSC) Table 139. TSC register map and reset values (continued) Offset Register CNT[13:0] TSC_IOG6CR 0x0048 Reset value CNT[13:0] TSC_IOG7CR 0x004C Reset value CNT[13:0] TSC_IOG8CR 0x0050 Reset value Refer to Section 2.2.2 on page 67 for the register boundary addresses. DocID024597 Rev 3 709/1693...
Page 710: Figure 170. Block Diagram
Random number generator (RNG) RM0351 Random number generator (RNG) 24.1 Introduction The RNG processor is a random number generator, based on a continuous analog noise, that provides a random 32-bit value to the host when read. The RNG passed the FIPS PUB 140-2 (2001 October 10) tests with a success ratio of 99%. 24.2 RNG main features •...
Page 711: Operation
RM0351 Random number generator (RNG) In parallel, the analog seed and the dedicated RNG_CLK clock are monitored. Status bits (in the RNG_SR register) indicate when an abnormal sequence occurs on the seed or when the frequency of the RNG_CLK clock is too low. An interrupt can be generated when an error is detected.
Page 712: Rng Registers
Random number generator (RNG) RM0351 24.4 RNG registers The RNG is associated with a control register, a data register and a status register. They have to be accessed by words (32 bits). 24.4.1 RNG control register (RNG_CR) Address offset: 0x00 Reset value: 0x0000 0000 Res.
Page 713: Rng Data Register (Rng_Dr)
RM0351 Random number generator (RNG) Bits 31:7 Reserved, must be kept at reset value Bit 6 SEIS: Seed error interrupt status This bit is set at the same time as SECS, it is cleared by writing it to 0. 0: No faulty sequence detected 1: One of the following faulty sequences has been detected: –...
Page 714: Table 140. Rng Register Map And Reset Map
Random number generator (RNG) RM0351 Bits 31:0 RNDATA: Random data 32-bit random data. 24.4.4 RNG register map Table 140 gives the RNG register map and reset values. Table 140. RNG register map and reset map Register name Offset reset value RNG_CR 0x00 Reset value...
Page 715: Introduction
RM0351 Advanced encryption standard hardware accelerator (AES) Advanced encryption standard hardware accelerator (AES) 25.1 Introduction The AES hardware accelerator can be used to both encipher and decipher data using AES algorithm. It is a fully compliant implementation of the following standard: •...
Page 716: Figure 171. Aes Block Diagram
Advanced encryption standard hardware accelerator (AES) RM0351 25.3 AES functional description Figure 171 shows the block diagram of the AES accelerator. Figure 171. AES block diagram The AES accelerator processes data blocks of 128-bits (4 words) using a key with a length of either 256 bits or 128 bits, and an initialization vector when CBC, CTR, GCM, GMAC or CMAC chaining mode is selected.
Page 717: Encryption And Derivation Keys
RM0351 Advanced encryption standard hardware accelerator (AES) in the AES_KEYRx registers and the AES is disabled by hardware. In this mode, the AES_KEYRx registers must not be read when AES is enabled and until the CCF flag is set to 1 by hardware. The status flag CCF in the AES_SR register is set once the computation phase is complete.
Page 718: Figure 172. Ecb Encryption Mode
Advanced encryption standard hardware accelerator (AES) RM0351 to switch the AES to mode 3 (decryption mode), there is no need to write the AES_KEYRx registers if their content corresponds to the derivation key (previously computed by mode 2). In mode 4 (key derivation + decryption), the AES_KEYRx registers contain only the encryption key.
Page 719: Figure 173. Ecb Decryption Mode
RM0351 Advanced encryption standard hardware accelerator (AES) Figure 173. ECB decryption mode 25.5.2 Cipher block chaining (CBC) In cipher-block chaining (CBC) mode, each block of plain text is XORed with the previous cipher text block before being encrypted. To make each message unique, an initialization vector (AES_IVRx) is used during the first block processing.
Page 720: Figure 174. Cbc Mode Encryption
Advanced encryption standard hardware accelerator (AES) RM0351 Figure 174. CBC mode encryption Figure 175. CBC mode decryption Note: When the AES is enabled, reading the AES_IVR returns the value 0x0000 0000. 720/1693 DocID024597 Rev 3...
Page 721 RM0351 Advanced encryption standard hardware accelerator (AES) Suspended mode for a given message It is possible to suspend a message if another message with a higher priority needs to be processed. After sending this highest priority message, the suspended message may be resumed in both encryption or decryption mode.
Page 722: Figure 176. Example Of Suspend Mode Management
Advanced encryption standard hardware accelerator (AES) RM0351 Figure 176. Example of suspend mode management 722/1693 DocID024597 Rev 3...
Page 723: Figure 177. Ctr Mode Encryption
RM0351 Advanced encryption standard hardware accelerator (AES) 25.5.3 Counter Mode (CTR) In counter mode, a 32-bit counter is used in addition to a nonce value for the XOR operation with the cipher text or plain text (refer to Figure 177 Figure 178).
Page 724: Figure 179. 32-Bit Counter + Nonce Organization
Advanced encryption standard hardware accelerator (AES) RM0351 The nonce value and 32-bit counter are accessible through the AES_IVRx register and organized like below in Figure 179: Figure 179. 32-bit counter + nonce organization In counter mode, the counter is incremented from the initialized value for each block to be processed in order to guarantee a unique sequence which is not repeated for a long time.
Page 725 RM0351 Advanced encryption standard hardware accelerator (AES) the size of the header on 64 bits and the size of the payload on 64 bits. During computation we have to distinguish between the blocks of the header and the blocks of the payload. Header •...
Page 726 Advanced encryption standard hardware accelerator (AES) RM0351 Repeat (p), (q), (r) and (s) until ciphering or deciphering of all the payload blocks. Alternatively, DMA may be used. GCM Final Phase: • In this last step, we generate the authentication tag. Choose the combination GCMPH[1:0] = 11 in AES_CR.
Page 727: Aes Cipher Message Authentication Code Mode (Cmac)
RM0351 Advanced encryption standard hardware accelerator (AES) Suspend mode during Payload phase: the user must respect the following steps: • Before interrupting the current message: Read 4 times the AES_DOUTR register. Make sure that busy flag is set to 0 (only in encryption mode, not necessary in decryption mode).
Page 728 Advanced encryption standard hardware accelerator (AES) RM0351 Note: In this stage, no output is provided in AES_DOUTR register. Set GCMPH=”01” in AES_CR to indicate that we are in the header phase. Enable the AES by setting EN bit in AES_CR. Insert B0 for first transfer, and then B for further transfers.
Page 729: Data Type
RM0351 Advanced encryption standard hardware accelerator (AES) To suspend mode CMAC during header phase, the user must respect the following steps: • Before interrupting the current message: Make sure that CCF flag in AES_SR is set to 1. Clear CCF flag in AES_SR register by setting CCFC bit to 1 in AES_CR. Save AES initialization vector registers AES_IVx and AES_SUSPxR registers in the memory (AES_IVx registers are modified during header phase) Disable AES processor by setting EN in AES_CR to 0.
Page 730: Figure 180. 128-Bit Block Construction According To The Data Type
Advanced encryption standard hardware accelerator (AES) RM0351 Figure 180. 128-bit block construction according to the data type 730/1693 DocID024597 Rev 3...
Page 731: Figure 181. 128-Bit Block Construction According To The Data Type (Continued)
RM0351 Advanced encryption standard hardware accelerator (AES) Figure 181. 128-bit block construction according to the data type (continued) 25.9 Operating modes 25.9.1 Mode 1: encryption Disable the AES by resetting EN bit in the AES_CR register. Configure the mode 1 by programming MODE[1:0] = 00 in the AES_CR register and select which type of chaining mode needs to be performed by programming the CHMOD[2:0] bits.
Page 732: Figure 182. Mode 1: Encryption With 128-Bit Key Length
Advanced encryption standard hardware accelerator (AES) RM0351 Figure 182. Mode 1: encryption with 128-bit key length 25.9.2 Mode 2: key derivation Disable the AES by resetting the EN bit in the AES_CR register. Configure mode 2 by programming MODE[1:0] = 01 in the AES_CR register. Note: CHMOD[2:0] bits are not significant in this case because this key derivation mode is independent from the chaining algorithm selected.
Page 733: Figure 184. Mode 3: Decryption With 128-Bit Key Length
RM0351 Advanced encryption standard hardware accelerator (AES) 25.9.3 Mode 3: decryption Disable the AES by resetting the EN bit in the AES_CR register. Configure mode 3 by programming MODE[1:0] = 10 in the AES_CR register and select which type of chaining mode needs to be performed by programming the CHMOD[2:0] bits.
Page 734: Figure 185. Mode 4: Key Derivation And Decryption With 128-Bit Key Length
Advanced encryption standard hardware accelerator (AES) RM0351 forced to CTR decryption mode if the software writes MODE[1:0] = 11 and CHMOD[2:0] = 010. Select key length 128-bit or 256-bit via KEYSIZE bits configuration in AES_CR register. Write the AES_KEYRx register with the encryption key. Write the AES_IVRx register if the CBC mode is selected.
Page 735: Figure 186. Dma Requests And Data Transfers During Input Phase (Aes_In)
RM0351 Advanced encryption standard hardware accelerator (AES) Note: For mode 2 (key derivation), access to the AES_KEYRx registers can be done by software using the CPU. No DMA channel is provided for this purpose. Consequently, the DMAINEN bit and DMAOUTEN bits in the AES_CR register have no effect during this mode. The CCF flag is not relevant when DMAOUTEN = 1 and software does not need to read it in this case.
Page 736: Table 141. Processing Time (In Clock Cycle)
Advanced encryption standard hardware accelerator (AES) RM0351 25.12 Processing time The following tables summarize the time required to process a 128-bit block for each mode of operation. Table 141. Processing time (in clock cycle) Computation Output Mode of operation Input phase Total phase phase...
Page 737: Table 144. Aes Interrupt Requests
RM0351 Advanced encryption standard hardware accelerator (AES) 25.13 AES interrupts Table 144. AES interrupt requests Enable Exit from Interrupt event Event flag control bit Wait AES computation completed flag CCFIE AES read error flag RDERR ERRIE AES write error flag WRERR ERRIE DocID024597 Rev 3...
Page 738: Aes Registers
Advanced encryption standard hardware accelerator (AES) RM0351 25.14 AES registers 25.14.1 AES control register (AES_CR) Address offset: 0x00 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SIZE Res. GCMPH[1:0] CCFIE CCFC MODE[1:0] ERRIE...
Page 739 RM0351 Advanced encryption standard hardware accelerator (AES) Bit 9 CCFIE: CCF flag interrupt enable An interrupt is generated if the CCF flag is set. 0: CCF interrupt disabled 1: CCF interrupt enabled Bit 8 ERRC: Error clear Writing 1 to this bit clears the RDERR and WRERR flags. This bit is always read low.
Page 740: Aes Status Register (Aes_Sr)
Advanced encryption standard hardware accelerator (AES) RM0351 25.14.2 AES status register (AES_SR) Address offset: 0x04 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 741 RM0351 Advanced encryption standard hardware accelerator (AES) Bit 2 WRERR: Write error flag This bit is set by hardware when an unexpected write operation to the AES_DINR register is detected (during computation or data output phase). An interrupt is generated if the ERRIE bit has been previously set in the AES_CR register.
Page 742: Aes Data Input Register (Aes_Dinr)
Advanced encryption standard hardware accelerator (AES) RM0351 25.14.3 AES data input register (AES_DINR) Address offset: 0x08 Reset value: 0x0000 0000 DINR[31:16] DINR[15:0] Bits 31:0 DINR[31:0]: Data input register This register must be written 4 times during the input phase: – In mode 1 (encryption), 4 words must be written which represent the plain text from MSB to LSB. –...
Page 743: Aes Key Register 0 (Aes_Keyr0) (Lsb: Key [31:0])
RM0351 Advanced encryption standard hardware accelerator (AES) 25.14.5 AES key register 0 (AES_KEYR0) (LSB: key [31:0]) Address offset: 0x10 Reset value: 0x0000 0000 KEYR0[31:16] KEYR0[15:0] Bits 31:0 KEYR0[31:0]: Data output register (LSB key [31:0]) This register must be written before the EN bit in the AES_CR register is set: In mode 1 (encryption), mode 2 (key derivation) and mode 4 (key derivation + decryption), the value to be written represents the encryption key from LSB, meaning key [31:0].
Page 744: Aes Key Register 2 (Aes_Keyr2) (Key [95:64])
Advanced encryption standard hardware accelerator (AES) RM0351 25.14.7 AES key register 2 (AES_KEYR2) (key [95:64]) Address offset: 0x18 Reset value: 0x0000 0000 KEYR2[31:16] KEYR2[15:0] Bits 31:0 KEYR2[31:0]: Data output register (key [95:64]) Refer to the description of AES_KEYR0. 25.14.8 AES key register 3 (AES_KEYR3) (MSB: key[127:96]) Address offset: 0x1C Reset value: 0x0000 0000 KEYR3[31:16]...
Page 745: Aes Initialization Vector Register 1 (Aes_Ivr1) (Ivr[63:32])
RM0351 Advanced encryption standard hardware accelerator (AES) Bits 31:0 IVR0[31:0]: initialization vector register (LSB IVR[31:0]) This register must be written before the EN bit in the AES_CR register is set: The register value has no meaning if: – The ECB mode (electronic codebook) is selected. –...
Page 746: Aes Initialization Vector Register 2 (Aes_Ivr2) (Ivr[95:64])
Advanced encryption standard hardware accelerator (AES) RM0351 25.14.11 AES initialization vector register 2 (AES_IVR2) (IVR[95:64]) Address offset: 0x28 Reset value: 0x0000 0000 IVR2[31:16] IVR2[15:0] Bits 31:0 IVR2[31:0]: Initialization vector register (IVR[95:64]) This register must be written before the EN bit in the AES_CR register is set: The register value has no meaning if: –...
Page 747: Aes Key Register 5 (Aes_Keyr5) (Key[191:160])
RM0351 Advanced encryption standard hardware accelerator (AES) KEYR431:16] KEYR4[15:0] Bits 31:0 KEYR4[31:0]: Data output register (key [159:128]) Same description as AES_KEYR0 for the key[159:128]. 25.14.14 AES key register 5 (AES_KEYR5) (key[191:160]) Address offset: 0x34 Reset value: 0x0000 0000 KEYR5[31:16] KEYR5[15:0] Bits 31:0 KEYR5[31:0]: Data output register (key [191:160]) Same description as AES_KEYR0 for the key[191:160].
Page 748 Advanced encryption standard hardware accelerator (AES) RM0351 KEYR731:16] KEYR7[15:0] Bits 31:0 KEYR7[31:0]: Data output register (MSB key [255:224]) Same description as AES_KEYR0 for the key[255:224]. Note: The key registers from 4 to 7 are used only when 256-bit key length is selected. These registers have no effect when 128-bit key length is selected (only key registers from 0 to 3 are used).
Page 749: Table 145. Aes Register Map
RM0351 Advanced encryption standard hardware accelerator (AES) 25.14.17 AES registers (AES_SUSPxR) (x = 0..7) Suspend Address offset: 0x040 (AES_SUSP0R) to 0x05C (AES_SUSP7R) Reset value: 0x0000 0000 These registers contain the complete internal register states of the AES processor when the GCM/GMAC is selected, and are useful when a suspend has to be done because a high- priority task has to use the AES processor while it is already in use by another task.
Page 750 Advanced encryption standard hardware accelerator (AES) RM0351 Table 145. AES register map Offset Register AES_KEYR0 AES_KEYR0[31:0] 0x0010 Reset value AES_KEYR1 AES_KEYR1[31:0] 0x0014 Reset value AES_KEYR2 AES_KEYR2[31:0] 0x0018 Reset value AES_KEYR3 AES_KEYR3[31:0] 0x001C Reset value AES_IVR0 AES_IVR0[31:0] 0x0020 Reset value AES_IVR1 AES_IVR1[31:0] 0x0024 Reset value...
Page 751 RM0351 Advanced encryption standard hardware accelerator (AES) Table 145. AES register map Offset Register AES_SUSP2R AES_SUSP2R[31:0] 0x0048 Reset value AES_SUSP3R AES_SUSP3R[31:0] 0x004C Reset value AES_SUSP4R AES_SUSP4R[31:0] 0x0050 Reset value AES_SUSP5R AES_SUSP5R[31:0] 0x0054 Reset value AES_SUSP6R AES_SUSP6R[31:0] 0x0058 Reset value AES_SUSP7R AES_SUSP7R[31:0] 0x005C Reset value...
Page 752: Tim1/Tim8 Introduction
Advanced-control timers (TIM1/TIM8) RM0351 Advanced-control timers (TIM1/TIM8) 26.1 TIM1/TIM8 introduction The advanced-control timers (TIM1/TIM8) consist of a 16-bit auto-reload counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Page 753: Figure 188. Advanced-Control Timer Block Diagram
RM0351 Advanced-control timers (TIM1/TIM8) Figure 188. Advanced-control timer block diagram DocID024597 Rev 3 753/1693...
Page 754: Tim1/Tim8 Functional Description
Advanced-control timers (TIM1/TIM8) RM0351 26.3 TIM1/TIM8 functional description 26.3.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit counter with its related auto-reload register. The counter can count up, down or both up and down. The counter clock can be divided by a prescaler.
Page 755: Figure 189. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0351 Advanced-control timers (TIM1/TIM8) Figure 189. Counter timing diagram with prescaler division change from 1 to 2 Figure 190. Counter timing diagram with prescaler division change from 1 to 4 DocID024597 Rev 3 755/1693...
Page 756: Counter Modes
Advanced-control timers (TIM1/TIM8) RM0351 26.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1.
Page 757: Figure 191. Counter Timing Diagram, Internal Clock Divided By 1
RM0351 Advanced-control timers (TIM1/TIM8) Figure 191. Counter timing diagram, internal clock divided by 1 Figure 192. Counter timing diagram, internal clock divided by 2 DocID024597 Rev 3 757/1693...
Page 758: Figure 193. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timers (TIM1/TIM8) RM0351 Figure 193. Counter timing diagram, internal clock divided by 4 Figure 194. Counter timing diagram, internal clock divided by N 758/1693 DocID024597 Rev 3...
Page 759: Figure 195. Counter Timing Diagram, Update Event When Arpe=0 (Timx_Arr Not Preloaded)
RM0351 Advanced-control timers (TIM1/TIM8) Figure 195. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) Figure 196. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) DocID024597 Rev 3 759/1693...
Page 760 Advanced-control timers (TIM1/TIM8) RM0351 Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. If the repetition counter is used, the update event (UEV) is generated after downcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR) + 1.
Page 761: Figure 197. Counter Timing Diagram, Internal Clock Divided By 1
RM0351 Advanced-control timers (TIM1/TIM8) Figure 197. Counter timing diagram, internal clock divided by 1 Figure 198. Counter timing diagram, internal clock divided by 2 DocID024597 Rev 3 761/1693...
Page 762: Figure 199. Counter Timing Diagram, Internal Clock Divided By 4
Advanced-control timers (TIM1/TIM8) RM0351 Figure 199. Counter timing diagram, internal clock divided by 4 Figure 200. Counter timing diagram, internal clock divided by N 762/1693 DocID024597 Rev 3...
Page 763: Figure 201. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
RM0351 Advanced-control timers (TIM1/TIM8) Figure 201. Counter timing diagram, update event when repetition counter is not used Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto- reload value down to 1 and generates a counter underflow event.
Page 764: Figure 202. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr = 0X6
Advanced-control timers (TIM1/TIM8) RM0351 DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 765: Figure 203. Counter Timing Diagram, Internal Clock Divided By 2
RM0351 Advanced-control timers (TIM1/TIM8) Figure 203. Counter timing diagram, internal clock divided by 2 Figure 204. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 DocID024597 Rev 3 765/1693...
Page 766: Figure 205. Counter Timing Diagram, Internal Clock Divided By N
Advanced-control timers (TIM1/TIM8) RM0351 Figure 205. Counter timing diagram, internal clock divided by N Figure 206. Counter timing diagram, update event with ARPE=1 (counter underflow) 766/1693 DocID024597 Rev 3...
Page 767: Figure 207. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow)
RM0351 Advanced-control timers (TIM1/TIM8) Figure 207. Counter timing diagram, Update event with ARPE=1 (counter overflow) 26.3.3 Repetition counter Section 26.3.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows/underflows. It is actually generated only when the repetition counter has reached zero.
Page 768: Figure 208. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
Advanced-control timers (TIM1/TIM8) RM0351 In Center aligned mode, for odd values of RCR, the update event occurs either on the overflow or on the underflow depending on when the RCR register was written and when the counter was launched: if the RCR was written before launching the counter, the UEV occurs on the overflow.
Page 769: Figure 209. External Trigger Input Block
RM0351 Advanced-control timers (TIM1/TIM8) 26.3.4 External trigger input The timer features an external trigger input ETR. It can be used as: • external clock (external clock mode 2, see Section 26.3.5) • trigger for the slave mode (see Section 26.3.26) •...
Page 770: Figure 211. Tim8 Etr Input Circuitry
Advanced-control timers (TIM1/TIM8) RM0351 Figure 211. TIM8 ETR input circuitry 770/1693 DocID024597 Rev 3...
Page 771: Figure 212. Control Circuit In Normal Mode, Internal Clock Divided By 1
RM0351 Advanced-control timers (TIM1/TIM8) 26.3.5 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin • External clock mode2: external trigger input ETR • Encoder mode Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed...
Page 772: Figure 213. Ti2 External Clock Connection Example
Advanced-control timers (TIM1/TIM8) RM0351 Figure 213. TI2 external clock connection example For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 773: Figure 214. Control Circuit In External Clock Mode 1
RM0351 Advanced-control timers (TIM1/TIM8) Figure 214. Control circuit in external clock mode 1 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 215 gives an overview of the external trigger input block.
Page 774: Figure 216. Control Circuit In External Clock Mode 2
Advanced-control timers (TIM1/TIM8) RM0351 As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
Page 775: Figure 217. Capture/Compare Channel (Example: Channel 1 Input Stage)
RM0351 Advanced-control timers (TIM1/TIM8) 26.3.6 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), an input stage for capture (with digital filter, multiplexing, and prescaler, except for channels 5 and 6) and an output stage (with comparator and output control). Figure 217 Figure 220 give an overview of one Capture/Compare channel.
Page 776: Figure 218. Capture/Compare Channel 1 Main Circuit
Advanced-control timers (TIM1/TIM8) RM0351 Figure 218. Capture/compare channel 1 main circuit Figure 219. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) 1. OCxREF, where x is the rank of the complementary channel 776/1693 DocID024597 Rev 3...
Page 777: Figure 220. Output Stage Of Capture/Compare Channel (Channel 4)
RM0351 Advanced-control timers (TIM1/TIM8) Figure 220. Output stage of capture/compare channel (channel 4) Figure 221. Output stage of capture/compare channel (channel 5, idem ch. 6) 1. Not available externally. The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register.
Page 778: Input Capture Mode
Advanced-control timers (TIM1/TIM8) RM0351 26.3.7 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 779: Figure 222. Pwm Input Mode Timing
RM0351 Advanced-control timers (TIM1/TIM8) 26.3.8 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 780: Output Compare Mode
Advanced-control timers (TIM1/TIM8) RM0351 forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=0 (OCx active high) => OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to 0100 in the TIMx_CCMRx register.
Page 781: Figure 223. Output Compare Mode, Toggle On Oc1
RM0351 Advanced-control timers (TIM1/TIM8) shadow register is updated only at the next update event UEV). An example is given in Figure 223. Figure 223. Output compare mode, toggle on OC1 26.3.11 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register.
Page 782: Figure 224. Edge-Aligned Pwm Waveforms (Arr=8)
Advanced-control timers (TIM1/TIM8) RM0351 PWM edge-aligned mode • Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 756. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <...
Page 783: Figure 225. Center-Aligned Pwm Waveforms (Arr=8)
RM0351 Advanced-control timers (TIM1/TIM8) Center-aligned mode (up/down counting) on page 763. Figure 225 shows some center-aligned PWM waveforms in an example where: • TIMx_ARR=8, • PWM mode is the PWM mode 1, • The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register.
Page 784: Asymmetric Pwm Mode
Advanced-control timers (TIM1/TIM8) RM0351 in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. • Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results.
Page 785: Figure 226. Generation Of 2 Phase-Shifted Pwm Signals With 50% Duty Cycle
RM0351 Advanced-control timers (TIM1/TIM8) Figure 226. Generation of 2 phase-shifted PWM signals with 50% duty cycle 26.3.13 Combined PWM mode Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and delay are determined by the two TIMx_CCRx registers.
Page 786: Figure 227. Combined Pwm Mode On Channel 1 And 3
Advanced-control timers (TIM1/TIM8) RM0351 Figure 227. Combined PWM mode on channel 1 and 3 26.3.14 Combined 3-phase PWM mode Combined 3-phase PWM mode allows one to three center-aligned PWM signals to be generated with a single programmable signal ANDed in the middle of the pulses. The OC5REF signal is used to define the resulting combined signal.
Page 787: Figure 228. 3-Phase Combined Pwm Signals With Multiple Trigger Pulses Per Period
RM0351 Advanced-control timers (TIM1/TIM8) Figure 228. 3-phase combined PWM signals with multiple trigger pulses per period The TRGO2 waveform shows how the ADC can be synchronized on given 3-phase PWM signals. Please refer to Section 26.3.27: ADC synchronization for more details. 26.3.15 Complementary outputs and dead-time insertion The advanced-control timers (TIM1/TIM8) can output two complementary signals and...
Page 788: Figure 229. Complementary Output With Dead-Time Insertion
Advanced-control timers (TIM1/TIM8) RM0351 Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the break circuit is present. There is one 10-bit dead-time generator for each channel. From a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are active high: •...
Page 789: Figure 231. Dead-Time Waveforms With Delay Greater Than The Positive Pulse
RM0351 Advanced-control timers (TIM1/TIM8) Figure 231. Dead-time waveforms with delay greater than the positive pulse The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register. Refer to Section 26.4.18: TIM1/TIM8 break and dead- time register (TIMx_BDTR) on page 836 for delay calculation.
Page 790 Advanced-control timers (TIM1/TIM8) RM0351 The output enable signal and output levels during break are depending on several control bits: – the MOE bit in TIMx_BDTR register allows to enable /disable the outputs by software and is reset in case of break or break2 event. –...
Page 791: Figure 232. Break And Break2 Circuitry Overview
RM0351 Advanced-control timers (TIM1/TIM8) All sources are ORed before entering the timer BRK or BRK2 inputs, as per Figure 232 below. Figure 232. Break and Break2 circuitry overview DocID024597 Rev 3 791/1693...
Page 792 Advanced-control timers (TIM1/TIM8) RM0351 When one of the breaks occurs (selected level on one of the break inputs): • The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state or even releasing the control to the GPIO controller (selected by the OSSI bit). This feature is enabled even if the MCU oscillator is off.
Page 793: Figure 233. Various Output Behavior In Response To A Break Event On Brk (Ossi = 1)
RM0351 Advanced-control timers (TIM1/TIM8) Figure 233. Various output behavior in response to a break event on BRK (OSSI = 1) DocID024597 Rev 3 793/1693...
Page 794: Table 146. Behavior Of Timer Outputs Versus Brk/Brk2 Inputs
Advanced-control timers (TIM1/TIM8) RM0351 The two break inputs have different behaviors on timer outputs: – The BRK input can either disable (inactive state) or force the PWM outputs to a predefined safe state. – BRK2 can only disable (inactive state) the PWM outputs. The BRK has a higher priority than BRK2 input, as described in Table 146.
Page 795: Figure 235. Pwm Output State Following Brk Assertion (Ossi=0)
RM0351 Advanced-control timers (TIM1/TIM8) Figure 235. PWM output state following BRK assertion (OSSI=0) 26.3.17 Bidirectional break inputs Beside regular digital break inputs and internal break events coming from the comparators, the timer 1 and 8 are featuring bidirectional break inputs/outputs combining the two sources, as represented on Figure 236.
Page 796: Figure 237. Clearing Timx Ocxref
Advanced-control timers (TIM1/TIM8) RM0351 OCREF_CLR_INPUT can be selected between the OCREF_CLR input and ETRF (ETR after the filter) by configuring the OCCS bit in the TIMx_SMCR register. The OCREF_CLR input is not connected (NC) in this product. The OCCS bit must be set to work in OCxREF clearing mode.
Page 797: Figure 238. 6-Step Generation, Com Example (Ossr=1)
RM0351 Advanced-control timers (TIM1/TIM8) 26.3.19 6-step PWM generation When complementary outputs are used on a channel, preload bits are available on the OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the COM commutation event. Thus you can program in advance the configuration for the next step and change the configuration of all the channels at the same time.
Page 798: Figure 239. Example Of One Pulse Mode
Advanced-control timers (TIM1/TIM8) RM0351 26.3.20 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 799: Retriggerable One Pulse Mode (Opm)
RM0351 Advanced-control timers (TIM1/TIM8) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 800: Figure 240. Retriggerable One Pulse Mode
Advanced-control timers (TIM1/TIM8) RM0351 Figure 240. Retriggerable one pulse mode 26.3.22 Encoder interface mode To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and SMS=’011’...
Page 801: Table 147. Counting Direction Versus Encoder Signals
RM0351 Advanced-control timers (TIM1/TIM8) Table 147. Counting direction versus encoder signals Level on TI1FP1 signal TI2FP2 signal opposite signal (TI1FP1 Active edge for TI2, Rising Falling Rising Falling TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count No Count...
Page 802: Figure 242. Example Of Encoder Interface Mode With Ti1Fp1 Polarity Inverted
Advanced-control timers (TIM1/TIM8) RM0351 Figure 242 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=’1’). Figure 242. Example of encoder interface mode with TI1FP1 polarity inverted. The timer, when configured in Encoder Interface mode provides information on the sensor’s current position.
Page 803: Figure 243. Measuring Time Interval Between Edges On 3 Signals
RM0351 Advanced-control timers (TIM1/TIM8) 26.3.24 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of an XOR gate, combining the two input pins TIMx_CH1 and TIMx_CH2. The XOR output can be used with all the timer input functions such as trigger or input capture.
Page 804 Advanced-control timers (TIM1/TIM8) RM0351 Example: you want to change the PWM configuration of your advanced-control timer TIM1 after a programmed delay each time a change occurs on the Hall inputs connected to one of the TIMx timers. • Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the TIMx_CR2 register to ‘1’, •...
Page 805: Figure 244. Example Of Hall Sensor Interface
RM0351 Advanced-control timers (TIM1/TIM8) Figure 244. Example of Hall sensor interface DocID024597 Rev 3 805/1693...
Page 806: Figure 245. Control Circuit In Reset Mode
Advanced-control timers (TIM1/TIM8) RM0351 26.3.26 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. They can be synchronized in several modes: Reset mode, Gated mode, and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 807: Figure 246. Control Circuit In Gated Mode
RM0351 Advanced-control timers (TIM1/TIM8) Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: • Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 808: Figure 247. Control Circuit In Trigger Mode
Advanced-control timers (TIM1/TIM8) RM0351 Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). • Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
Page 809: Figure 248. Control Circuit In External Clock Mode 2 + Trigger Mode
RM0351 Advanced-control timers (TIM1/TIM8) Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: – ETF = 0000: no filter – ETPS=00: prescaler disabled – ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2.
Page 810: Adc Synchronization
Advanced-control timers (TIM1/TIM8) RM0351 26.3.27 ADC synchronization The timer can generate an ADC triggering event with various internal signals, such as reset, enable or compare events. It is also possible to generate a pulse issued by internal edge detectors, such as: –...
Page 811: Debug Mode
RM0351 Advanced-control timers (TIM1/TIM8) Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers. –...
Page 812: Tim1/Tim8 Registers
Advanced-control timers (TIM1/TIM8) RM0351 26.4 TIM1/TIM8 registers Refer to for a list of abbreviations used in register descriptions. 26.4.1 TIM1/TIM8 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 UIFRE Res. Res. Res. Res. Res. CKD[1:0] ARPE CMS[1:0] UDIS Bits 15:12 Reserved, must be kept at reset value.
Page 813: Tim1/Tim8 Control Register 2 (Timx_Cr2)
RM0351 Advanced-control timers (TIM1/TIM8) Bit 3 OPM: One pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled.
Page 814 Advanced-control timers (TIM1/TIM8) RM0351 Bits 31:24 Reserved, must be kept at reset value. Bits 23:20 MMS2[3:0]: Master mode selection 2 These bits allow the information to be sent to ADC for synchronization (TRGO2) to be selected. The combination is as follows: 0000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO2).
Page 815 RM0351 Advanced-control timers (TIM1/TIM8) Bit 11 OIS2N: Output Idle state 2 (OC2N output) Refer to OIS1N bit Bit 10 OIS2: Output Idle state 2 (OC2 output) Refer to OIS1 bit Bit 9 OIS1N: Output Idle state 1 (OC1N output) 0: OC1N=0 after a dead-time when MOE=0 1: OC1N=1 after a dead-time when MOE=0 Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been programmed (LOCK bits in TIMx_BDTR register).
Page 816: Tim1/Tim8 Slave Mode Control Register (Timx_Smcr)
Advanced-control timers (TIM1/TIM8) RM0351 Bit 2 CCUS: Capture/compare control update selection 0: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only 1: When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when an rising edge occurs on TRGI Note: This bit acts only on channels that have a complementary output.
Page 817 RM0351 Advanced-control timers (TIM1/TIM8) Bits 13:12 ETPS[1:0]: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4...
Page 818: Table 148. Timx Internal Trigger Connection
Advanced-control timers (TIM1/TIM8) RM0351 Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 819: Tim1/Tim8 Dma/Interrupt Enable Register (Timx_Dier)
RM0351 Advanced-control timers (TIM1/TIM8) 26.4.4 TIM1/TIM8 DMA/interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 Res. COMDE CC4DE CC3DE CC2DE CC1DE COMIE CC4IE CC3IE CC2IE CC1IE Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled 1: Trigger DMA request enabled Bit 13 COMDE: COM DMA request enable...
Page 820: Tim1/Tim8 Status Register (Timx_Sr)
Advanced-control timers (TIM1/TIM8) RM0351 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 26.4.5...
Page 821 RM0351 Advanced-control timers (TIM1/TIM8) Bit 8 B2IF: Break 2 interrupt flag This flag is set by hardware as soon as the break 2 input goes active. It can be cleared by software if the break 2 input is not active. 0: No break event occurred.
Page 822: Tim1/Tim8 Event Generation Register (Timx_Egr)
Advanced-control timers (TIM1/TIM8) RM0351 Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...
Page 823: Tim1/Tim8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0351 Advanced-control timers (TIM1/TIM8) Bit 2 CC2G: Capture/Compare 2 generation Refer to CC1G description Bit 1 CC1G: Capture/Compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
Page 824 Advanced-control timers (TIM1/TIM8) RM0351 Bit 15 OC2CE: Output Compare 2 clear enable Bits 14:12 OC2M[2:0]: Output Compare 2 mode Bit 11 OC2PE: Output Compare 2 preload enable Bit 10 OC2FE: Output Compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input.
Page 825 RM0351 Advanced-control timers (TIM1/TIM8) Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 826 Advanced-control timers (TIM1/TIM8) RM0351 Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 827 RM0351 Advanced-control timers (TIM1/TIM8) Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 828: Tim1/Tim8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
Advanced-control timers (TIM1/TIM8) RM0351 26.4.8 TIM1/TIM8 capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 0000 Refer to the above CCMR1 register description. Res. Res. Res. Res. Res. Res. Res. OC4M[3] Res. Res. Res. Res. Res. Res. Res. OC3M[3] Res.
Page 829: Tim1/Tim8 Capture/Compare Enable Register (Timx_Ccer)
RM0351 Advanced-control timers (TIM1/TIM8) Input capture mode Bits 31:16 Reserved, must be kept at reset value. Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3...
Page 830 Advanced-control timers (TIM1/TIM8) RM0351 Bit 15 CC4NP: Capture/Compare 4 complementary output polarity Refer to CC1NP description Bit 14 Reserved, must be kept at reset value. Bit 13 CC4P: Capture/Compare 4 output polarity Refer to CC1P description Bit 12 CC4E: Capture/Compare 4 output enable Refer to CC1E description Bit 11 CC3NP: Capture/Compare 3 complementary output polarity Refer to CC1NP description...
Page 831 RM0351 Advanced-control timers (TIM1/TIM8) Bit 1 CC1P: Capture/Compare 1 output polarity CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select the active polarity of TI1FP1 and TI2FP1 for trigger or capture operations. 00: non-inverted/rising edge.
Page 832: Table 149. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
Advanced-control timers (TIM1/TIM8) RM0351 Table 149. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state Output disabled (not driven by the timer: Hi-Z) OCx=0, OCxN=0 Output disabled (not driven OCxREF + Polarity...
Page 833: Tim1/Tim8 Counter (Timx_Cnt)
RM0351 Advanced-control timers (TIM1/TIM8) 26.4.10 TIM1/TIM8 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 UIFCPY Res. Res. Res. Res. Res. Res. Res. Re s. Res. Res. Res. Res. Res. Res. Res. CNT[15:0] Bit 31 UIFCPY: UIF copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in the TIMxCR1 is reset, bit 31 is reserved and read at 0.
Page 834: Tim1/Tim8 Repetition Counter Register (Timx_Rcr)
Advanced-control timers (TIM1/TIM8) RM0351 26.4.13 TIM1/TIM8 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 REP[15:0] Bits 15:0 REP[15:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Page 835: Tim1/Tim8 Capture/Compare Register 2 (Timx_Ccr2)
RM0351 Advanced-control timers (TIM1/TIM8) 26.4.15 TIM1/TIM8 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
Page 836: Tim1/Tim8 Capture/Compare Register 4 (Timx_Ccr4)
Advanced-control timers (TIM1/TIM8) RM0351 26.4.17 TIM1/TIM8 capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 CCR4[15:0] Bits 15:0 CCR4[15:0]: Capture/Compare value If channel CC4 is configured as output: CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC4PE).
Page 837 RM0351 Advanced-control timers (TIM1/TIM8) Bit 24 BK2E: Break 2 enable This bit enables the complete break 2 protection (including all sources connected to bk_acth and BKIN sources, as per). 0: Break2 function disabled 1: Break2 function enabled Note: The BRKIN2 must only be used with OSSR = OSSI = 1. Note: This bit cannot be modified when LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 838 Advanced-control timers (TIM1/TIM8) RM0351 Bit 15 MOE: Main output enable This bit is cleared asynchronously by hardware as soon as one of the break inputs is active (BRK or BRK2). It is set by software or automatically depending on the AOE bit. It is acting only on the channels which are configured in output.
Page 839 RM0351 Advanced-control timers (TIM1/TIM8) Bit 10 OSSI: Off-state selection for Idle mode This bit is used when MOE=0 due to a break event or by a software write, on channels configured as outputs. See OC/OCN enable description for more details (Section 26.4.9: TIM1/TIM8 capture/compare enable register (TIMx_CCER) on page 829).
Page 840: Tim1/Tim8 Dma Control Register (Timx_Dcr)
Advanced-control timers (TIM1/TIM8) RM0351 26.4.19 TIM1/TIM8 DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0] Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the length of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e.
Page 841: Tim1/Tim8 Dma Address For Full Transfer (Timx_Dmar)
RM0351 Advanced-control timers (TIM1/TIM8) 26.4.20 TIM1/TIM8 DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 DMAB[15:0] Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA...
Page 842: Tim8 Option Register 1 (Tim8_Or1)
Advanced-control timers (TIM1/TIM8) RM0351 Bits 1:0 ETR_ADC1_RMP: External trigger remap on ADC1 analog watchdog 00 : TIM1_ETR is not connected to ADC1 AWDx. This configuration must be selected when the ETR comes from the I/O. 01 : TIM1_ETR is connected to ADC1 AWD1. 10 : TIM1_ETR is connected to ADC1 AWD2.
Page 843: Tim1/Tim8 Capture/Compare Mode Register 3 (Timx_Ccmr3)
RM0351 Advanced-control timers (TIM1/TIM8) 26.4.23 TIM1/TIM8 capture/compare mode register 3 (TIMx_CCMR3) Address offset: 0x54 Reset value: 0x0000 0000 Refer to the above CCMR1 register description. Channels 5 and 6 can only be configured in output. Res. Res. Res. Res. Res. Res.
Page 844 Advanced-control timers (TIM1/TIM8) RM0351 Bit 31 GC5C3: Group Channel 5 and Channel 3 Distortion on Channel 3 output: 0: No effect of OC5REF on OC3REFC 1: OC3REFC is the logical AND of OC3REFC and OC5REF This bit can either have immediate effect or be preloaded and taken into account after an update event (if preload feature is selected in TIMxCCMR2).
Page 845: Tim1/Tim8 Capture/Compare Register 6 (Timx_Ccr6)
RM0351 Advanced-control timers (TIM1/TIM8) 26.4.25 TIM1/TIM8 capture/compare register 6 (TIMx_CCR6) Address offset: 0x5C Reset value: 0x0000 CCR6[15:0] Bits 15:0 CCR6[15:0]: Capture/Compare 6 value CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC6PE).
Page 846 Advanced-control timers (TIM1/TIM8) RM0351 Bit 10 BKCMP1P: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active high 1: COMP1 input is active low Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 847: Tim1 Option Register 3 (Tim1_Or3)
RM0351 Advanced-control timers (TIM1/TIM8) 26.4.27 TIM1 option register 3 (TIM1_OR3) Address offset: 0x64 Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BK2C BK2C BK2IN BK2DFB BK2CMP BK2CM Res. Res.
Page 848: Tim8 Option Register 2 (Tim8_Or2)
Advanced-control timers (TIM1/TIM8) RM0351 Bit 1 BK2CMP1E: BRK2 COMP1 enable This bit enables the COMP1 for the timer’s BRK2 input. COMP1 output is ‘ORed’ with the other BRK2 sources. 0: COMP1 input disabled 1: COMP1 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 849 RM0351 Advanced-control timers (TIM1/TIM8) Bit 10 BKCMP1P: BRK COMP1 input polarity This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP1 input is active high 1: COMP1 input is active low Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 850: Tim8 Option Register 3 (Tim8_Or3)
Advanced-control timers (TIM1/TIM8) RM0351 26.4.29 TIM8 option register 3 (TIM8_OR3) Address offset: 0x64 Reset value: 0x0000 0001 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BK2C BK2C BK2IN BK2DFB BK2CMP BK2CM Res. Res.
Page 851: Table 150. Tim1 Register Map And Reset Values
RM0351 Advanced-control timers (TIM1/TIM8) Bit 1 BK2CMP1E: BRK2 COMP1 enable This bit enables the COMP1 for the timer’s BRK2 input. COMP1 output is ‘ORed’ with the other BRK2 sources. 0: COMP1 input disabled 1: COMP1 input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 852 Advanced-control timers (TIM1/TIM8) RM0351 Table 150. TIM1 register map and reset values (continued) Offset Register TIM1_CCMR1 OC2M OC1M Output [2:0] [2:0] [1:0] [1:0] Compare mode Reset value 0x18 TIM1_CCMR1 IC2F[3:0] IC1F[3:0] Input Capture [1:0] [1:0] [1:0] [1:0] mode Reset value TIM1_CCMR2 OC4M OC3M...
Page 853 RM0351 Advanced-control timers (TIM1/TIM8) Table 150. TIM1 register map and reset values (continued) Offset Register TIM1_BDTR BK2F[3:0] BKF[3:0] DT[7:0] 0x44 [1:0] Reset value TIM1_DCR DBL[4:0] DBA[4:0] 0x48 Reset value TIM1_DMAR DMAB[15:0] 0x4C Reset value TIM1_OR1 0x50 Reset value TIM1_CCMR3 OC6M OC5M Output [2:0]...
Page 854: Table 151. Tim8 Register Map And Reset Values
Advanced-control timers (TIM1/TIM8) RM0351 26.4.31 TIM8 register map TIM8 registers are mapped as 16-bit addressable registers as described in the table below: Table 151. TIM8 register map and reset values Offset Register TIM8_CR1 [1:0] [1:0] 0x00 Reset value TIM8_CR2 MMS2[3:0] [2:0] 0x04 Reset value...
Page 855 RM0351 Advanced-control timers (TIM1/TIM8) Table 151. TIM8 register map and reset values (continued) Offset Register TIM8_CNT CNT[15:0] 0x24 Reset value TIM8_PSC PSC[15:0] 0x28 Reset value TIM8_ARR ARR[15:0] 0x2C Reset value TIM8_RCR REP[15:0] 0x30 Reset value TIMx_CCR1 CCR1[15:0] 0x34 Reset value TIM8_CCR2 CCR2[15:0] 0x38...
Page 856 Advanced-control timers (TIM1/TIM8) RM0351 Table 151. TIM8 register map and reset values (continued) Offset Register TIM8_CCMR3 OC6M OC5M Output [2:0] [2:0] 0x54 Compare mode Reset value TIM8_CCR5 CCR5[15:0] 0x58 Reset value TIM8_CCR6 CCR6[15:0] 0x5C Reset value ETRSEL TIM8_OR2 [2:0] 0x60 Reset value TIM8_OR3 0x64...
Page 857: Tim2/Tim3/Tim4/Tim5 Introduction
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.1 TIM2/TIM3/TIM4/TIM5 introduction The general-purpose timers consist of a 16-bit or 32-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).
Page 858: Figure 249. General-Purpose Timer Block Diagram
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 249. General-purpose timer block diagram 858/1693 DocID024597 Rev 3...
Page 859: Tim2/Tim3/Tim4/Tim5 Functional Description
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.3 TIM2/TIM3/TIM4/TIM5 functional description 27.3.1 Time-base unit The main block of the programmable timer is a 16-bit/32-bit counter with its related auto- reload register. The counter can count up, down or both up and down but also down or both up and down.
Page 860: Figure 250. Counter Timing Diagram With Prescaler Division Change From 1 To 2
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 250. Counter timing diagram with prescaler division change from 1 to 2 Figure 251. Counter timing diagram with prescaler division change from 1 to 4 860/1693 DocID024597 Rev 3...
Page 861: Figure 252. Counter Timing Diagram, Internal Clock Divided By 1
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
Page 862: Figure 253. Counter Timing Diagram, Internal Clock Divided By 2
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 253. Counter timing diagram, internal clock divided by 2 Figure 254. Counter timing diagram, internal clock divided by 4 862/1693 DocID024597 Rev 3...
Page 863: Figure 255. Counter Timing Diagram, Internal Clock Divided By N
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 255. Counter timing diagram, internal clock divided by N Figure 256. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) DocID024597 Rev 3 863/1693...
Page 864: Figure 257. Counter Timing Diagram, Update Event When Arpe=1 (Timx_Arr Preloaded)
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 257. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event.
Page 865: Figure 258. Counter Timing Diagram, Internal Clock Divided By 1
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 258. Counter timing diagram, internal clock divided by 1 Figure 259. Counter timing diagram, internal clock divided by 2 DocID024597 Rev 3 865/1693...
Page 866: Figure 260. Counter Timing Diagram, Internal Clock Divided By 4
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 260. Counter timing diagram, internal clock divided by 4 Figure 261. Counter timing diagram, internal clock divided by N 866/1693 DocID024597 Rev 3...
Page 867: Figure 262. Counter Timing Diagram, Update Event When Repetition Counter
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 262. Counter timing diagram, Update event when repetition counter is not used Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto- reload value down to 1 and generates a counter underflow event.
Page 868: Figure 263. Counter Timing Diagram, Internal Clock Divided By 1, Timx_Arr=0X6
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): •...
Page 869: Figure 264. Counter Timing Diagram, Internal Clock Divided By 2
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 264. Counter timing diagram, internal clock divided by 2 Figure 265. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 1. Center-aligned mode 2 or 3 is used with an UIF on overflow. DocID024597 Rev 3 869/1693...
Page 870: Figure 266. Counter Timing Diagram, Internal Clock Divided By N
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 266. Counter timing diagram, internal clock divided by N Figure 267. Counter timing diagram, Update event with ARPE=1 (counter underflow) 870/1693 DocID024597 Rev 3...
Page 871: Figure 268. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow)
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 268. Counter timing diagram, Update event with ARPE=1 (counter overflow) 27.3.3 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin (TIx) •...
Page 872: Figure 269. Control Circuit In Normal Mode, Internal Clock Divided By 1
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 269. Control circuit in normal mode, internal clock divided by 1 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 270.
Page 873: Figure 271. Control Circuit In External Clock Mode 1
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the TIMx_CCMR1 register. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). Note: The capture prescaler is not used for triggering, so you don’t need to configure it.
Page 874: Figure 272. External Trigger Input Block
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 272. External trigger input block For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register...
Page 875: Figure 273. Control Circuit In External Clock Mode 2
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 273. Control circuit in external clock mode 2 27.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control).
Page 876: Figure 274. Capture/Compare Channel (Example: Channel 1 Input Stage)
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 274. Capture/compare channel (example: channel 1 input stage) The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 275. Capture/compare channel 1 main circuit 876/1693 DocID024597 Rev 3...
Page 877: Figure 276. Output Stage Of Capture/Compare Channel (Channel 1)
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Figure 276. Output stage of capture/compare channel (channel 1) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
Page 878 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 detected (sampled at f frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. Select the edge of the active transition on the TI1 channel by writing the CC1P and CC1NP and CC1NP bits to 000 in the TIMx_CCER register (rising edge in this case). Program the input prescaler.
Page 879: Figure 277. Pwm Input Mode Timing
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.3.6 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 880: Forced Output Mode
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 27.3.7 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (ocxref/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register.
Page 881: Figure 278. Output Compare Mode, Toggle On Oc1
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 278.
Page 882: Figure 279. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 cleared by an external event through the ETR signal until the next PWM period), the OCREF signal is asserted only: • When the result of the comparison or • When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from the “frozen”...
Page 883 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Downcounting mode on page 864. In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then ocxref is held at ‘1.
Page 884: Figure 280. Center-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 280. Center-aligned PWM waveforms (ARR=8) Hints on using center-aligned mode: • When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register.
Page 885: Figure 281. Generation Of 2 Phase-Shifted Pwm Signals With 50% Duty Cycle
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.3.10 Asymmetric PWM mode Asymmetric mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the frequency is determined by the value of the TIMx_ARR register, the duty cycle and the phase-shift are determined by a pair of TIMx_CCRx registers.
Page 886: Figure 282. Combined Pwm Mode On Channels 1 And 3
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 When a given channel is used as combined PWM channel, its secondary channel must be configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the other in Combined PWM mode 2). Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant bit is not contiguous with the 3 least significant ones.
Page 887: Figure 283. Clearing Timx Ocxref
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) The OCxREF signal for a given channel can be reset by applying a high level on the ETRF input (OCxCE enable bit set to 1 in the corresponding TIMx_CCMRx register). OCxREF remains low until the next update event (UEV) occurs. This function can be used only in the output compare and PWM modes.
Page 888: Figure 284. Example Of One-Pulse Mode
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 27.3.13 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 889: Retriggerable One Pulse Mode (Opm)
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 890: Figure 285. Retriggerable One Pulse Mode
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 285. Retriggerable one pulse mode 27.3.15 Encoder interface mode To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and TI2 edges.
Page 891: Table 152. Counting Direction Versus Encoder Signals
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Table 152. Counting direction versus encoder signals Level on opposite TI1FP1 signal TI2FP2 signal Active edge signal (TI1FP1 for Rising Falling Rising Falling TI2, TI2FP2 for TI1) High Down No Count No Count Counting on TI1 only Down No Count No Count...
Page 892: Figure 287. Example Of Encoder Interface Mode With Ti1Fp1 Polarity Inverted
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Figure 287. Example of encoder interface mode with TI1FP1 polarity inverted The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode.
Page 893: Figure 288. Control Circuit In Reset Mode
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.3.18 Timers and external trigger synchronization The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated.
Page 894: Figure 289. Control Circuit In Gated Mode
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register.
Page 895: Figure 290. Control Circuit In Trigger Mode
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=110 in TIMx_SMCR register. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set.
Page 896: Figure 291. Control Circuit In External Clock Mode 2 + Trigger Mode
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input.
Page 897: Figure 293. Gating Tim2 With Oc1Ref Of Tim3
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) For example, you can configure TIM3 to act as a prescaler for TIM2. Refer to Figure 292. To do this: Configure TIM3 in master mode so that it outputs a periodic trigger signal on each update event UEV. If you write MMS=010 in the TIM3_CR2 register, a rising edge is output on TRGO1 each time an update event is generated.
Page 898: Figure 294. Gating Tim2 With Enable Of Tim3
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 in the timer counters. The timers can easily be reset by software using the UG bit in the TIMx_EGR registers. In the next example, we synchronize TIM3 and TIM2. TIM3 is the master and starts from 0. TIM2 is the slave and starts from 0xE7.
Page 899: Figure 295. Triggering Tim2 With Update Of Tim3
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Configure TIM3 master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIM3_CR2 register). Configure the TIM3 period (TIM3_ARR registers). Configure TIM2 to get the input trigger from TIM3 (TS=010 in the TIM2_SMCR register).
Page 900: Figure 297. Triggering Tim3 And Tim2 With Tim3 Ti1 Input
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 aligned, TIM3 must be configured in Master/Slave mode (slave with respect to TI1, master with respect to TIM2): Configure TIM3 master mode to send its Enable as trigger output (MMS=001 in the TIM3_CR2 register). Configure TIM3 slave mode to get the input trigger from TI1 (TS=100 in the TIM3_SMCR register).
Page 901: Debug Mode
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers (either in half-words or in bytes). The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA transfers (when read/write access are done through the TIMx_DMAR address).
Page 902: Tim2/Tim3/Tim4/Tim5 Registers
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 27.4 TIM2/TIM3/TIM4/TIM5 registers Refer to Section 1.1 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 27.4.1 TIMx control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 Res.
Page 903 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled.
Page 904: Timx Control Register 2 (Timx_Cr2)
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 27.4.2 TIMx control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1S MMS[2:0] CCDS Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) Section 26.3.25: Interfacing with Hall sensors on page 803...
Page 905: Timx Slave Mode Control Register (Timx_Smcr)
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.4.3 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMS[3] ETPS[1:0] ETF[3:0] TS[2:0] OCCS SMS[2:0] Bits 31:17 Reserved, must be kept at reset value. Bit 16 SMS[3]: Slave mode selection - bit 3 Refer to SMS description - bits 2:0 Bit 15 ETP: External trigger polarity...
Page 906 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 907: Table 153. Timx Internal Trigger Connection
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Bits 6:4 TS: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0). reserved 001: Internal Trigger 1 (ITR1). 010: Internal Trigger 2 (ITR2). 011: Internal Trigger 3 (ITR3). reserved 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2)
Page 908 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Table 153. TIMx internal trigger connection (continued) Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) ITR3 (TS = 011) TIM4 TIM1 TIM2 TIM3 TIM8 TIM5 TIM2 TIM3 TIM4 TIM8 1. Depends on the bit ITR1_RMP in TIM2_OR1 register. 908/1693 DocID024597 Rev 3...
Page 909: Timx Dma/Interrupt Enable Register (Timx_Dier)
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 Res. Res. CC4DE CC3DE CC2DE CC1DE Res. Res. CC4IE CC3IE CC2IE CC1IE Bit 15 Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled.
Page 910: Timx Status Register (Timx_Sr)
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled.
Page 911 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Bit 2 CC2IF: Capture/Compare 2 interrupt flag Refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description) and in retriggerable one pulse mode.
Page 912: Timx Event Generation Register (Timx_Egr)
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 27.4.6 TIMx event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CC4G CC3G CC2G CC1G Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 913: Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 914 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 915 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 916 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 917: Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. OC4M OC3M Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Page 918: Timx Capture/Compare Enable Register (Timx_Ccer)
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4...
Page 919 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Bit 15 CC4NP: Capture/Compare 4 output Polarity. Refer to CC1NP description Bit 14 Reserved, must be kept at reset value. Bit 13 CC4P: Capture/Compare 4 output Polarity. Refer to CC1P description Bit 12 CC4E: Capture/Compare 4 output enable. refer to CC1E description Bit 11 CC3NP: Capture/Compare 3 output Polarity.
Page 920: Table 154. Output Control Bit For Standard Ocx Channels
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Bit 2 Reserved, must be kept at reset value. Bit 1 CC1P: Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.
Page 921: Timx Prescaler (Timx_Psc)
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Bit 31 Value depends on IUFREMAP in TIMx_CR1. If UIFREMAP = 0 CNT[31]: Most significant bit of counter value (on TIM2 and TIM5) Reserved on other timers If UIFREMAP = 1 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register Bits 30:16 CNT[30:16]: Most significant part counter value (on TIM2 and TIM5) Bits 15:0 CNT[15:0]: Least significant part of counter value 27.4.11...
Page 922: Timx Capture/Compare Register 2 (Timx_Ccr2)
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 CCR1[15:0] Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2 and TIM5) Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE).
Page 923: Timx Capture/Compare Register 4 (Timx_Ccr4)
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) CCR3[15:0] Bits 31:16 CCR3[31:16]: High Capture/Compare 3 value (on TIM2 and TIM5) Bits 15:0 CCR3[15:0]: Low Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC3PE).
Page 924: Timx Dma Control Register (Timx_Dcr)
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 27.4.17 TIMx DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0] Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address).
Page 925: Tim2 Option Register 1 (Tim2_Or1)
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.4.19 TIM2 option register 1 (TIM2_OR1) Address offset: 0x50 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ETR1_ ITR1_ Res. Res. Res. Res. Res. Res. Res.
Page 926: Tim3 Option Register 2 (Tim3_Or2)
General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SEL2 ETRSEL[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Bits 31:17 Reserved, must be kept at reset value. Bits 16:14 ETRSEL[2:0]: ETR source selection These bits select the ETR input source.
Page 927: Table 155. Tim2/Tim3/Tim4/Tim5 Register Map And Reset Values
RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) 27.4.23 TIMx register map TIMx registers are mapped as described in the table below: Table 155. TIM2/TIM3/TIM4/TIM5 register map and reset values Offset Register TIMx_CR1 [1:0] [1:0] 0x00 Reset value TIMx_CR2 MMS[2:0] 0x04 Reset value ETPS TIMx_SMCR ETF[3:0] TS[2:0]...
Page 928 General-purpose timers (TIM2/TIM3/TIM4/TIM5) RM0351 Table 155. TIM2/TIM3/TIM4/TIM5 register map and reset values (continued) Offset Register CNT[30:16] TIMx_CNT CNT[15:0] (TIM2 and TIM5 only, reserved on the other timers) 0x24 Reset value TIMx_PSC PSC[15:0] 0x28 Reset value ARR[31:16] TIMx_ARR ARR[15:0] (TIM2 and TIM5 only, reserved on the other timers) 0x2C Reset value 0x30...
Page 929 RM0351 General-purpose timers (TIM2/TIM3/TIM4/TIM5) Table 155. TIM2/TIM3/TIM4/TIM5 register map and reset values (continued) Offset Register ETRSEL TIM2_OR2 [2:0] 0x60 Reset value ETRSEL TIM3_OR2 [2:0] 0x60 Reset value Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses.
Page 930: Tim15/16/17 Introduction
General-purpose timers (TIM15/16/17) RM0351 General-purpose timers (TIM15/16/17) 28.1 TIM15/16/17 introduction The TIM15/16/17 timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with dead-time insertion).
Page 931: Tim16 And Tim17 Main Features
RM0351 General-purpose timers (TIM15/16/17) 28.3 TIM16 and TIM17 main features The TIM16 and TIM17 timers include the following features: • 16-bit auto-reload upcounter • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535 •...
Page 932: Figure 298. Tim15 Block Diagram
General-purpose timers (TIM15/16/17) RM0351 Figure 298. TIM15 block diagram 1. The internal break event source can be: A clock failure event generated by CSS. For further information on the CSS, refer to Section 6.2.9: Clock security system (CSS) A PVD output SRAM parity error signal ®...
Page 933: Figure 299. Tim16 And Tim17 Block Diagram
RM0351 General-purpose timers (TIM15/16/17) Figure 299. TIM16 and TIM17 block diagram 1. The internal break event source can be: A clock failure event generated by CSS. For further information on the CSS, refer to Section 6.2.9: Clock security system (CSS) A PVD output SRAM parity error signal ®...
Page 934: Tim15/16/17 Functional Description
General-purpose timers (TIM15/16/17) RM0351 28.4 TIM15/16/17 functional description 28.4.1 Time-base unit The main block of the programmable advanced-control timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software.
Page 935: Figure 300. Counter Timing Diagram With Prescaler Division Change From 1 To 2
RM0351 General-purpose timers (TIM15/16/17) Figure 300. Counter timing diagram with prescaler division change from 1 to 2 Figure 301. Counter timing diagram with prescaler division change from 1 to 4 DocID024597 Rev 3 935/1693 1009...
Page 936: Counter Modes
General-purpose timers (TIM15/16/17) RM0351 28.4.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. If the repetition counter is used, the update event (UEV) is generated after upcounting is repeated for the number of times programmed in the repetition counter register (TIMx_RCR).
Page 937: Figure 302. Counter Timing Diagram, Internal Clock Divided By 1
RM0351 General-purpose timers (TIM15/16/17) Figure 302. Counter timing diagram, internal clock divided by 1 Figure 303. Counter timing diagram, internal clock divided by 2 DocID024597 Rev 3 937/1693 1009...
Page 938: Figure 304. Counter Timing Diagram, Internal Clock Divided By 4
General-purpose timers (TIM15/16/17) RM0351 Figure 304. Counter timing diagram, internal clock divided by 4 Figure 305. Counter timing diagram, internal clock divided by N 938/1693 DocID024597 Rev 3...
Page 939: Preloaded)
RM0351 General-purpose timers (TIM15/16/17) Figure 306. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) Figure 307. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) DocID024597 Rev 3 939/1693 1009...
Page 940: Repetition Counter
General-purpose timers (TIM15/16/17) RM0351 28.4.3 Repetition counter Section 28.4.1: Time-base unit describes how the update event (UEV) is generated with respect to the counter overflows. It is actually generated only when the repetition counter has reached zero. This can be useful when generating PWM signals. This means that data are transferred from the preload registers to the shadow registers (TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx capture/compare registers in compare mode) every N counter overflows, where N is the...
Page 941: Figure 308. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings
RM0351 General-purpose timers (TIM15/16/17) Figure 308. Update rate examples depending on mode and TIMx_RCR register settings 28.4.4 Clock selection The counter clock can be provided by the following clock sources: • Internal clock (CK_INT) • External clock mode1: external input pin •...
Page 942: Figure 309. Control Circuit In Normal Mode, Internal Clock Divided By 1
General-purpose timers (TIM15/16/17) RM0351 only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 309 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.
Page 943: Figure 311. Control Circuit In External Clock Mode 1
RM0351 General-purpose timers (TIM15/16/17) For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register.
Page 944: Figure 312. Capture/Compare Channel (Example: Channel 1 Input Stage)
General-purpose timers (TIM15/16/17) RM0351 Figure 312. Capture/compare channel (example: channel 1 input stage) The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 313. Capture/compare channel 1 main circuit 944/1693 DocID024597 Rev 3...
Page 945: Figure 314. Output Stage Of Capture/Compare Channel (Channel 1)
RM0351 General-purpose timers (TIM15/16/17) Figure 314. Output stage of capture/compare channel (channel 1) Figure 315. Output stage of capture/compare channel (channel 2 for TIM15) The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register.
Page 946: Input Capture Mode
General-purpose timers (TIM15/16/17) RM0351 28.4.6 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled.
Page 947: Figure 316. Pwm Input Mode Timing
RM0351 General-purpose timers (TIM15/16/17) 28.4.7 PWM input mode (only for TIM15) This mode is a particular case of input capture mode. The procedure is the same except: • Two ICx signals are mapped on the same TIx input. • These 2 ICx signals are active on edges with opposite polarity. •...
Page 948: Forced Output Mode
General-purpose timers (TIM15/16/17) RM0351 28.4.8 Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register.
Page 949: Figure 317. Output Compare Mode, Toggle On Oc1
RM0351 General-purpose timers (TIM15/16/17) Procedure Select the counter clock (internal, external, prescaler). Write the desired data in the TIMx_ARR and TIMx_CCRx registers. Set the CCxIE bit if an interrupt request is to be generated. Select the output mode. For example: –...
Page 950: Figure 318. Edge-Aligned Pwm Waveforms (Arr=8)
General-purpose timers (TIM15/16/17) RM0351 As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register.
Page 951: Figure 319. Combined Pwm Mode On Channel 1 And 2
RM0351 General-purpose timers (TIM15/16/17) by the two TIMx_CCRx registers. The resulting signals, OCxREFC, are made of an OR or AND logical combination of two reference PWMs: • OC1REFC (or OC2REFC) is controlled by the TIMx_CCR1 and TIMx_CCR2 registers Combined PWM mode can be selected independently on two channels (one OCx output per pair of CCR registers) by writing ‘1100’...
Page 952: Figure 320. Complementary Output With Dead-Time Insertion
General-purpose timers (TIM15/16/17) RM0351 28.4.12 Complementary outputs and dead-time insertion The TIM15/16/17 general-purpose timers can output one complementary signal and manage the switching-off and switching-on of the outputs. This time is generally known as dead-time and you have to adjust it depending on the devices you have connected to the outputs and their characteristics (intrinsic delays of level- shifters, delays due to power switches...) You can select the polarity of the outputs (main output OCx or complementary OCxN)
Page 953: Figure 321. Dead-Time Waveforms With Delay Greater Than The Negative Pulse
RM0351 General-purpose timers (TIM15/16/17) Figure 321. Dead-time waveforms with delay greater than the negative pulse. Figure 322. Dead-time waveforms with delay greater than the positive pulse. The dead-time delay is the same for each of the channels and is programmable with the DTG bits in the TIMx_BDTR register.
Page 954: Using The Break Function
General-purpose timers (TIM15/16/17) RM0351 28.4.13 Using the break function The purpose of the break function is to protect power switches driven by PWM signals generated with the TIM15/16/17 timers. The break input is usually connected to fault outputs of power stages and 3-phase inverters. When activated, the break circuitry shuts down the PWM outputs and forces them to a predefined safe state.
Page 955: Figure 323. Break Circuitry Overview
RM0351 General-purpose timers (TIM15/16/17) Break events can also be generated by software using BG bit in the TIMx_EGR register. All sources are ORed before entering the timer BRK inputs, as per Figure 323 below. Figure 323. Break circuitry overview Note: An asynchronous (clockless) operation is only guaranteed when the programmable filter is disabled.
Page 956 General-purpose timers (TIM15/16/17) RM0351 active level together. Note that because of the resynchronization on MOE, the dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles). – If OSSI=0 then the timer releases the enable outputs (taken over by the AFIO controller which forces a Hi-Z state) else the enable outputs remain or become high as soon as one of the CCxE or CCxNE bits is high.
Page 957: Figure 324. Output Behavior In Response To A Break
RM0351 General-purpose timers (TIM15/16/17) Figure 324. Output behavior in response to a break DocID024597 Rev 3 957/1693 1009...
Page 958: Figure 325. Example Of One Pulse Mode
General-purpose timers (TIM15/16/17) RM0351 28.4.14 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller.
Page 959: Uif Bit Remapping
RM0351 General-purpose timers (TIM15/16/17) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). • The t is defined by the value written in the TIMx_CCR1 register. DELAY • The t is defined by the difference between the auto-reload value and the compare PULSE value (TIMx_ARR - TIMx_CCR1).
Page 960: Figure 326. Measuring Time Interval Between Edges On 2 Signals
General-purpose timers (TIM15/16/17) RM0351 28.4.16 Timer input XOR function (TIM15 only) The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the two input pins TIMx_CH1 and TIMx_CH2. The XOR output can be used with all the timer input functions such as trigger or input capture.
Page 961: Figure 327. Control Circuit In Reset Mode
RM0351 General-purpose timers (TIM15/16/17) 28.4.17 External trigger synchronization (TIM15 only) The TIM timers are linked together internally for timer synchronization or chaining. The TIM15 timer can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Page 962: Figure 328. Control Circuit In Gated Mode
General-purpose timers (TIM15/16/17) RM0351 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000).
Page 963: Figure 329. Control Circuit In Trigger Mode
RM0351 General-purpose timers (TIM15/16/17) Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000).
Page 964: Debug Mode
General-purpose timers (TIM15/16/17) RM0351 The DBL[4:0] bits in the TIMx_DCR register set the DMA burst length. The timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address), i.e. the number of transfers (either in half-words or in bytes). The DBA[4:0] bits in the TIMx_DCR registers define the DMA base address for DMA transfers (when read/write access are done through the TIMx_DMAR address).
Page 965: Tim15 Registers
RM0351 General-purpose timers (TIM15/16/17) 28.5 TIM15 registers Refer to Section 1.1 for a list of abbreviations used in register descriptions. 28.5.1 TIM15 control register 1 (TIM15_CR1) Address offset: 0x00 Reset value: 0x0000 UIF RE- Res. Res. Res. Res. Res. CKD[1:0] ARPE Res.
Page 966: Tim15 Control Register 2 (Tim15_Cr2)
General-purpose timers (TIM15/16/17) RM0351 Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt if enabled. These events can be: –...
Page 967 RM0351 General-purpose timers (TIM15/16/17) Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 pins are connected to the TI1 input (XOR combination) Bits 6:4 MMS[1:0]: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO).
Page 968: Tim15 Slave Mode Control Register (Tim15_Smcr)
General-purpose timers (TIM15/16/17) RM0351 28.5.3 TIM15 slave mode control register (TIM15_SMCR) Address offset: 0x08 Reset value: 0x0000 0000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMS[3] Res. Res. Res. Res. Res. Res. Res.
Page 969: Table 156. Timx Internal Trigger Connection
RM0351 General-purpose timers (TIM15/16/17) Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description.
Page 970: Tim15 Status Register (Tim15_Sr)
General-purpose timers (TIM15/16/17) RM0351 Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled 1: CC2 DMA request enabled Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled 1: CC1 DMA request enabled Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled 1: Update DMA request enabled...
Page 971 RM0351 General-purpose timers (TIM15/16/17) Bit 8 Reserved, must be kept at reset value. Bit 7 BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active. 0: No break event occurred 1: An active level has been detected on the break input Bit 6 TIF: Trigger interrupt flag...
Page 972: Tim15 Event Generation Register (Tim15_Egr)
General-purpose timers (TIM15/16/17) RM0351 28.5.6 TIM15 event generation register (TIM15_EGR) Address offset: 0x14 Reset value: 0x0000 Res. Res. Res. Res. Res. Res. Res. Res. COMG Res. Res. CC2G CC1G Bits 15:8 Reserved, must be kept at reset value. Bit 7 BG: Break generation This bit is set by software in order to generate an event, it is automatically cleared by hardware.
Page 973: Tim15 Capture/Compare Mode Register 1 (Tim15_Ccmr1)
RM0351 General-purpose timers (TIM15/16/17) 28.5.7 TIM15 capture/compare mode register 1 (TIM15_CCMR1) Address offset: 0x18 Reset value: 0x0000 0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode.
Page 974 General-purpose timers (TIM15/16/17) RM0351 Bits 6:4 OC1M: Output Compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 975 RM0351 General-purpose timers (TIM15/16/17) Bit 3 OC1PE: Output Compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register.
Page 976: Tim15 Capture/Compare Enable Register (Tim15_Ccer)
General-purpose timers (TIM15/16/17) RM0351 Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at f 0001: f...
Page 977 RM0351 General-purpose timers (TIM15/16/17) Bit 5 CC2P: Capture/Compare 2 output polarity Refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable Refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high 1: OC1N active low CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1.
Page 978: Table 157. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
General-purpose timers (TIM15/16/17) RM0351 Bit 0 CC1E: Capture/Compare 1 output enable CC1 channel configured as output: 0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits. 1: On - OC1 signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits.
Page 979: Tim15 Counter (Tim15_Cnt)
RM0351 General-purpose timers (TIM15/16/17) 28.5.9 TIM15 counter (TIM15_CNT) Address offset: 0x24 Reset value: 0x0000 0000 CNT[15:0] Bit 31 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit in the TIMx_ISR register. Bits 30:16 Reserved, must be kept at reset value. Bits 15:0 CNT[15:0]: Counter value 28.5.10 TIM15 prescaler (TIM15_PSC)
Page 980: Tim15 Repetition Counter Register (Tim15_Rcr)
General-purpose timers (TIM15/16/17) RM0351 28.5.12 TIM15 repetition counter register (TIM15_RCR) Address offset: 0x30 Reset value: 0x0000 REP[7:0] Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.
Page 981: Tim15 Capture/Compare Register 2 (Tim15_Ccr2)
RM0351 General-purpose timers (TIM15/16/17) 28.5.14 TIM15 capture/compare register 2 (TIM15_CCR2) Address offset: 0x38 Reset value: 0x0000 CCR2[15:0] Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE).
Page 982 General-purpose timers (TIM15/16/17) RM0351 Bit 13 BKP: Break polarity 0: Break input BRK is active low 1: Break input BRK is active high Note: 1: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 983: Tim15 Dma Control Register (Tim15_Dcr)
RM0351 General-purpose timers (TIM15/16/17) Bits 7:0 DTG[7:0]: Dead-time generator setup This bit-field defines the duration of the dead-time inserted between the complementary outputs. DT correspond to this duration. DTG[7:5]=0xx => DT=DTG[7:0]x t with t DTG[7:5]=10x => DT=(64+DTG[5:0])xt with T =2xt DTG[7:5]=110 =>...
Page 984: Tim15 Option Register 1 (Tim15_Or1)
General-purpose timers (TIM15/16/17) RM0351 Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).
Page 985 RM0351 General-purpose timers (TIM15/16/17) Bit 11 BKCMP2P: BRK COMP2 input polarity This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP polarity bit. 0: COMP2 input is active low 1: COMP2 input is active high Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 986: Table 158. Tim15 Register Map And Reset Values
General-purpose timers (TIM15/16/17) RM0351 Bit 0 BKINE: BRK BKIN input enable This bit enables the BKIN alternate function input for the timer’s BRK input. BKIN input is ‘ORed’ with the other BRK sources. 0: BKIN input disabled 1: BKIN input enabled Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits in TIMx_BDTR register).
Page 987 RM0351 General-purpose timers (TIM15/16/17) Table 158. TIM15 register map and reset values (continued) Offset Register TIM15_CCER 0x20 Reset value TIM15_CNT CNT[15:0] 0x24 Reset value TIM15_PSC PSC[15:0] 0x28 Reset value TIM15_ARR ARR[15:0] 0x2C Reset value TIM15_RCR REP[7:0] 0x30 Reset value TIM15_CCR1 CCR1[15:0] 0x34 Reset value...
Page 988 General-purpose timers (TIM15/16/17) RM0351 Table 158. TIM15 register map and reset values (continued) Offset Register TIM15_OR2 0x60 Reset value Refer to Section 2.2 on page 65 for the register boundary addresses. 988/1693 DocID024597 Rev 3...
Page 989: Tim16&Tim17 Registers
RM0351 General-purpose timers (TIM15/16/17) 28.6 TIM16&TIM17 registers Refer to Section 1.1 on page 61 for a list of abbreviations used in register descriptions. 28.6.1 TIM16&TIM17 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 CKD[1:0] ARPE UDIS REM- Bits 15:12 Reserved, must be kept at reset value. Bit 11 UIFREMAP: UIF status bit remapping 0: No remapping.
Page 990: Tim16&Tim17 Control Register 2 (Timx_Cr2)
General-purpose timers (TIM15/16/17) RM0351 Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow –...
Page 991: Tim16&Tim17 Dma/Interrupt Enable Register (Timx_Dier)
RM0351 General-purpose timers (TIM15/16/17) Bit 0 CCPC: Capture/compare preloaded control 0: CCxE, CCxNE and OCxM bits are not preloaded 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set. Note: This bit acts only on channels that have a complementary output.
Page 992: Tim16&Tim17 Status Register (Timx_Sr)
General-purpose timers (TIM15/16/17) RM0351 28.6.4 TIM16&TIM17 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 CC1OF COMIF CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits 15:10 Reserved, must be kept at reset value. Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode.
Page 993: Tim16&Tim17 Event Generation Register (Timx_Egr)
RM0351 General-purpose timers (TIM15/16/17) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...
Page 994: Tim16&Tim17 Capture/Compare Mode Register 1 (Timx_Ccmr1)
General-purpose timers (TIM15/16/17) RM0351 Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Reinitialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected).
Page 995 RM0351 General-purpose timers (TIM15/16/17) Bits 6:4 OC1M[2:0]: Output Compare 1 mode (bits 2 to 0) These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits.
Page 996: Tim16&Tim17 Capture/Compare Enable Register (Timx_Ccer)
General-purpose timers (TIM15/16/17) RM0351 Input capture mode Bits 31:8 Reserved, must be kept at reset value. Bits 7:4 IC1F[3:0]: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1.
Page 997 RM0351 General-purpose timers (TIM15/16/17) Bits 15:4 Reserved, must be kept at reset value. Bit 3 CC1NP: Capture/Compare 1 complementary output polarity CC1 channel configured as output: 0: OC1N active high 1: OC1N active low CC1 channel configured as input: This bit is used in conjunction with CC1P to define the polarity of TI1FP1 and TI2FP1. Refer to the description of CC1P.
Page 998: Table 159. Output Control Bits For Complementary Ocx And Ocxn Channels With Break Feature
General-purpose timers (TIM15/16/17) RM0351 Table 159. Output control bits for complementary OCx and OCxN channels with break feature Control bits Output states MOE bit OSSI bit OSSR bit CCxE bit CCxNE bit OCx output state OCxN output state Output Disabled (not driven by the timer: Hi-Z) OCx=0 OCxN=0, OCxN_EN=0 Output Disabled (not driven...
Page 999: Tim16&Tim17 Prescaler (Timx_Psc)
RM0351 General-purpose timers (TIM15/16/17) Bit 31 UIFCPY: UIF Copy This bit is a read-only copy of the UIF bit of the TIMx_ISR register. If the UIFREMAP bit in TIMx_CR1 is reset, bit 31 is reserved and read as 0. Bits 30:16 Reserved, must be kept at reset value. Bits 15:0 CNT[15:0]: Counter value 28.6.9 TIM16&TIM17 prescaler (TIMx_PSC)
Page 1000: Tim16&Tim17 Repetition Counter Register (Timx_Rcr)
General-purpose timers (TIM15/16/17) RM0351 28.6.11 TIM16&TIM17 repetition counter register (TIMx_RCR) Address offset: 0x30 Reset value: 0x0000 REP[7:0] Bits 15:8 Reserved, must be kept at reset value. Bits 7:0 REP[7:0]: Repetition counter value These bits allow the user to set-up the update rate of the compare registers (i.e. periodic transfers from preload to active registers) when preload registers are enable, as well as the update interrupt generation rate, if this interrupt is enable.

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