Aes Registers - ST STM32L4x6 Reference Manual

Advanced encryption standard hardware accelerator (AES)
25.14

AES registers

25.14.1 AES control register (AES_CR)
Address offset: 0x00
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
DMA
Res. GCMPH[1:0]
OUT
EN
rw rw rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 KEYSIZE: Key size selection
0: 128 bit key length
1: 256 bit key length
The operation mode must only be changed if the AES is disabled. Writing these bits while the AES is
enabled is forbidden in order to avoid unpredictable AES behavior.
Bits 17, 15 Reserved, must be kept at reset value.
Bits 14:13 GCMPH[1:0]: Used only for GCM, GMAC and CMAC algorithms and has no effect when other
algorithms are selected
00: GCM init Phase
01: GCM header phase
10: GCM payload phase
11: GCM final phase
Note: GCM init phase and GCM payload phase must not be used when CMAC is selected, else AES
peripheral behavior is not guaranteed.
Bit 12 DMAOUTEN: Enable DMA management of data output phase
0: DMA (during data output phase) disabled
1: DMA (during data output phase) enabled
If the DMAOUTEN bit is set, DMA requests are generated for the output data phase in mode 1, 3 or
4. This bit has no effect in mode 2 (key derivation).
Bit 11 DMAINEN: Enable DMA management of data input phase
0: DMA (during data input phase) disabled
1: DMA (during data input phase) enabled
If the DMAINEN bit is set, DMA requests are generated for the data input phase in mode 1, 3 or 4. This
bit has no action in mode 2 (key derivation).
Bit 10 ERRIE: Error interrupt enable
An interrupt is generated if at least one of the both flags RDERR or WRERR is set.
0: Error interrupt disabled
1: Error interrupt enabled
738/1693
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
DMA
CCFIE
ERRIE ERRC
INEN
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DocID024597 Rev 3
23 22 21 20
Res. Res. Res. Res.
7 6 5
CCFC
CHMOD[1:0]
rw rw rw rw
19 18 17
KEY
Res. Res.
SIZE
rw
4 3 2 1
MODE[1:0]
DATATYPE[1:0]
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RM0351
16
CH
MOD
[2]
rw
0
EN
rw