Opamp Registers - ST STM32L4x6 Reference Manual

RM0351
Mode
Standby
Shutdown
20.5

OPAMP registers

20.5.1 OPAMP1 control/status register (OPAMP1_CSR)
Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
OPA_
Res. Res.
RANGE
rw
15 14 13
CAL USER CAL
CALON
OUT TRIM SEL
r rw rw
Bit 31 OPA_RANGE: Operational amplifier power supply range for stability
All AOP must be in power down to allow AOP-RANGE bit write. It applies to all AOP
embedded in the product.
Bits 30:16 Reserved, must be kept at reset value.
Bit 15 CALOUT: Operational amplifier calibration output
During calibration mode offset is trimmed when this signal toggle.
Bit 14 USERTRIM: allows to switch from 'factory' AOP offset trimmed values to AOP offset 'user'
trimmed values
This bit is active for both mode normal and low-power.
Bit 13 CALSEL: Calibration selection
Bit 12 CALON: Calibration mode enabled
Bit 11 Reserved, must be kept at reset value.
Bit 10 VP_SEL: Non inverted input selection
Table 118. Effect of low-power modes on the OPAMP
The OPAMP registers are powered down and must be re-initialized after
exiting Standby or Shutdown mode.
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
VP_
Res. VM_SEL
SEL
rw rw rw
0: Low range (VDDA < 2.4V)
1: High range (VDDA > 2.4V)
0: 'factory' trim code used
1: 'user' trim code used
0: NMOS calibration (200mV applied on OPAMP inputs)
1: PMOS calibration (VDDA-200mV applied on OPAMP inputs)
0: Normal mode
1: Calibration mode (all switches opened by HW)
0: GPIO connected to VINP
1: DAC connected to VINP
DocID024597 Rev 3
Description
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
Res. Res. PGA_GAIN
rw rw
Operational amplifiers (OPAMP)
20 19 18
Res. Res. Res.
4 3 2
OPAMODE
rw rw w
17 16
Res. Res.
1 0
OPA
OPAEN
LPM
rw rw
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