ST STM32L4x6 Reference Manual page 539

RM0351
Table 100. ADC register map and reset values for each ADC (offset=0x000
Offset Register
ADCx_JSQR
0x4C
Reset value
0x50-
Reserved
0x5C
ADCx_OFR1
0x60
Reset value 0
ADCx_OFR2
0x64
Reset value 0
ADCx_OFR3
0x68
Reset value 0
ADCx_OFR4
0x6C
Reset value 0
0x70-
Reserved
0x7C
ADCx_JDR1
0x80
Reset value
ADCx_JDR2
0x84
Reset value
ADCx_JDR3
0x88
Reset value
ADCx_JDR4
0x8C
Reset value
0x8C-
Reserved
0x9C
ADCx_AWD2CR
0xA0
Reset value
ADCx_AWD3CR
0xA4
Reset value
0xA8-
Reserved
0xAC
ADCx_DIFSEL
0xB0
Reset value
for master ADC, 0x100 for slave ADC) (continued)
JSQ4[4:0] JSQ3[4:0]
0 0 0 0 0 0 0 0
OFFSET1_
CH[4:0]
0 0 0 0 0
OFFSET2_
CH[4:0]
0 0 0 0 0
OFFSET3_
CH[4:0]
0 0 0 0 0
OFFSET4_
CH[4:0]
0 0 0 0 0
DocID024597 Rev 3
Analog-to-digital converters (ADC)
JSQ2[4:0]
0 0 0 0 0 0 0
Res.
Res.
0 0 0
0 0 0
0 0 0
0 0 0
Res.
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
JEXTSEL
JSQ1[4:0]
[3:0]
0 0 0 0 0 0 0 0 0
OFFSET1[11:0]
0 0 0 0 0 0 0 0
OFFSET2[11:0]
0 0 0 0 0 0 0 0
OFFSET3[11:0]
0 0 0 0 0 0 0 0
OFFSET4[11:0]
0 0 0 0 0 0 0 0
JDATA1[15:0]
0 0 0 0 0 0 0 0 0
JDATA2[15:0]
0 0 0 0 0 0 0 0 0
JDATA3[15:0]
0 0 0 0 0 0 0 0 0
JDATA4[15:0]
0 0 0 0 0 0 0 0 0
AWD2CH[18:0]
0 0 0 0 0 0 0 0 0
AWD3CH[18:0]
0 0 0 0 0 0 0 0 0
DIFSEL[18:0]
0 0 0 0 0 0 0 0 0
JL[1:0]
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
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