Independent Data Register (Crc_Idr) - ST STM32L4x6 Reference Manual

Cyclic redundancy check calculation unit (CRC)
13.4.2

Independent data register (CRC_IDR)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28
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15 14 13 12
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13.4.3 Control register (CRC_CR)
Bits 31:0 IDR[31:0]: General-purpose 32-bit data register bits
These bits can be used as a temporary storage location for one byte.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register
Address offset: 0x08
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:8 Reserved, must be kept cleared.
Bit 7 REV_OUT: Reverse output data
This bit controls the reversal of the bit order of the output data.
0: Bit order not affected
1: Bit-reversed output format
Bits 6:5 REV_IN[1:0]: Reverse input data
These bits control the reversal of the bit order of the input data
00: Bit order not affected
01: Bit reversal done by byte
10: Bit reversal done by half-word
11: Bit reversal done by word
340/1693
27 26 25
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11 10 9
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28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
DocID024597 Rev 3
24 23 22 21
IDR[31:16]
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8 7 6 5
IDR[15:0]
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24 23 22 21
Res. Res. Res. Res.
8 7 6 5
REV_
Res. REV_IN[1:0]
OUT
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20 19 18 17
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4 3 2 1
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20 19 18 17
Res. Res. Res. Res.
4 3 2 1
POLYSIZE[1:0] Res. Res.
rw rw
RM0351
16
rw
0
rw
16
Res.
0
RESET
rs