Gpio Port Bit Reset Register (Gpiox_Brr) (X =A..h) - ST STM32L4x6 Reference Manual

RM0351
7.4.10 GPIO alternate function high register (GPIOx_AFRH)
(x = A..H)
Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
AFSEL15[3:0]
rw rw rw
15 14 13
AFSEL11[3:0]
rw rw rw
Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 8..15)
These bits are written by software to configure alternate function I/Os
AFSELy selection:
7.4.11

GPIO port bit reset register (GPIOx_BRR) (x =A..H)

Address offset: 0x28
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
BR15 BR14 BR13 BR12
w w w
Bits 31:16 Reserved
Bits 15:0 BRy: Port x Reset bit y (y= 0..15)
These bits are write-only. A read to these bits returns the value 0x0000
7.4.12 GPIO port analog switch control register (GPIOx_ASCR)(x = A..H)
Address offset: 0x2C
Reset value: 0x0000 0000
28 27 26 25
AFSEL14[3:0]
rw rw rw rw
12 11 10 9
AFSEL10[3:0]
rw rw rw rw
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
BR11 BR10 BR9
w w w w
0: No action on the corresponding ODx bit
1: Reset the corresponding ODx bit
24 23 22
AFSEL13[3:0]
rw rw rw
8 7 6
AFSEL9[3:0]
rw rw rw
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15
24 23 22
Res. Res. Res.
8 7 6
BR8 BR7 BR6
w w w
DocID024597 Rev 3
General-purpose I/Os (GPIO)
21 20 19 18
AFSEL12[3:0]
rw rw rw rw
5 4 3 2
AFSEL8[3:0]
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
BR5 BR4 BR3 BR2
w w w w
17 16
rw rw
1 0
rw rw
17 16
Res. Res.
1 0
BR1 BR0
w w
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