Apb2 Peripheral Reset Register (Rcc_Apb2Rstr) - ST STM32L4x6 Reference Manual

RM0351
6.4.15

APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x40
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
USART
TIM8 SPI1
Res. 1
RST RST
RST
rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 DFSDMRST: Digital filters for sigma-delta modulators (DFSDM) reset
Bit 23 Reserved, must be kept at reset value.
Bit 22 SAI2RST: Serial audio interface 2 (SAI2) reset
Bit 21 SAI1RST: Serial audio interface 1 (SAI1) reset
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 TIM17RST: TIM17 timer reset
Bit 17 TIM16RST: TIM16 timer reset
Bit 16 TIM15RST: TIM15 timer reset
Bit 15 Reserved, must be kept at reset value.
28 27 26 25
Res. Res. Res.
12 11 10 9
SDMMC
TIM1
1 Res.
RST
RST
rw rw rw
Set and cleared by software.
0: No effect
1: Reset DFSDM
Set and cleared by software.
0: No effect
1: Reset SAI2
Set and cleared by software.
0: No effect
1: Reset SAI1
Set and cleared by software.
0: No effect
1: Reset TIM17 timer
Set and cleared by software.
0: No effect
1: Reset TIM16 timer
Set and cleared by software.
0: No effect
1: Reset TIM15 timer
24 23 22
DFSDM SAI2
Res.
RST RST
rw rw
8 7 6
Res. Res. Res.
DocID024597 Rev 3
Reset and clock control (RCC)
21 20 19 18
SAI1 TIM17
Res. Res.
RST RST
rw rw
5 4 3 2
Res. Res. Res. Res.
17 16
TIM16 TIM15R
RST ST
rw rw
1 0
SYS
Res. CFG
RST
rw
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