Power control (PWR)
15
14
13
12
PU15
PU14
PU13
PU12
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 PUy: Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.
5.4.11
Power Port B pull-down control register (PWR_PDCRB)
Address offset: 0x2C.
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
PD15
PD14
PD13
PD12
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:5 PDy: Port B pull-down bit y (y=5..15)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
Bit 4 Reserved, must be kept at reset value.
Bits 3:0 PDy: Port B pull-down bit y (y=0..3)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.
5.4.12
Power Port C pull-up control register (PWR_PUCRC)
Address offset: 0x30.
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
PWRRST bit in the RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
31
30
29
28
Res.
Res.
Res.
Res.
170/1693
11
10
9
8
PU11
PU10
PU9
PU8
rw
rw
rw
rw
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
PD11
PD10
PD9
PD8
rw
rw
rw
rw
27
26
25
24
Res.
Res.
Res.
Res.
DocID024597 Rev 3
7
6
5
4
PU7
PU6
PU5
PU4
rw
rw
rw
rw
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
PD7
PD6
PD5
Res.
rw
rw
rw
23
22
21
20
Res.
Res.
Res.
Res.
RM0351
3
2
1
0
PU3
PU2
PU1
PU0
rw
rw
rw
rw
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
PD3
PD2
PD1
PD0
rw
rw
rw
rw
19
18
17
16
Res.
Res.
Res.
Res.
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