Backup Domain Control Register (Rcc_Bdcr) - ST STM32L4x6 Reference Manual

Reset and clock control (RCC)
6.4.29

Backup domain control register (RCC_BDCR)

Address offset: 0x90
Reset value: 0x0000 0000, reset by Backup domain Reset, except LSCOSEL, LSCOEN
and BDRST which are reset only by Backup domain power-on reset.
Access: 0 ≤wait state ≤3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Note: The bits of the
domain. As a result, after Reset, these bits are write-protected and the DBP bit in the
Section 5.4.1: Power control register 1 (PWR_CR1)
modified. Refer to
information. These bits (except LSCOSEL, LSCOEN and BDRST) are only reset after a
Backup domain Reset (see
Reset will not have any effect on these bits.
31 30 29
Res. Res. Res. Res.
15 14 13
RTC
Res. Res. Res.
EN
rw
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 LSCOSEL: Low speed clock output selection
Set and cleared by software.
0: LSI clock selected
1: LSE clock selected
Bit 24 LSCOEN: Low speed clock output enable
Set and cleared by software.
0: Low speed clock output (LSCO) disable
1: Low speed clock output (LSCO) enable
Bits 23:17 Reserved, must be kept at reset value.
Bit 16 BDRST: Backup domain software reset
Set and cleared by software.
0: Reset not activated
1: Resets the entire Backup domain
Bit 15 RTCEN: RTC clock enable
Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, must be kept at reset value.
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Backup domain control register (RCC_BDCR)
Section 5.1.5: Battery backup domain on page 136
Section 6.1.3: Backup domain
28 27 26 25
LSCO
Res. Res.
SEL
rw
12 11 10 9
Res. Res. RTCSEL[1:0]
rw
DocID024597 Rev 3
has to be set before these can be
24 23 22 21
LSCO
Res. Res. Res.
EN
rw
8 7 6 5
LSE LSE
Res.
CSSD CSSON
rw r rw
are outside of the V
for further
reset). Any internal or external
20 19 18
Res. Res. Res. Res.
4 3 2
LSE LSE
LSEDRV[1:0]
BYP RDY
rw rw rw
RM0351
CORE
17 16
BDRST
rw
1 0
LSEON
r rw