Extremes Detector - ST STM32L4x6 Reference Manual

RM0351
There is an upcounting counter on each input channel which is counting consecutive 0's or
1's on serial data receiver outputs. A counter is restarted if there is a change in the data
stream received - 1 to 0 or 0 to 1 change of data signal. If this counter reaches a short-circuit
threshold register value (SCDT[7:0] bits in DFSDM_AWSCDyR register), then a short-circuit
event is invoked. Each input channel has its short-circuit detector. Any channel can be
selected to be continuously monitored by setting the SCDEN bit (in DFSDM_CHCFGyR1
register) and it has its own short-circuit detector settings (threshold value in SCDT[7:0] bits,
status bit SCDF[7:0], status clearing bits CLRSCDF[7:0]). Status flag SCDF[y] is cleared
also by hardware when corresponding channel y is disabled (CHEN[y] = 0).
On each channel, a short-circuit detector event can be assigned to break output signal
DFSDM_BREAK[3:0]. There are four break outputs to be assigned to a short-circuit detector
event. The break signal assignment to a given channel short-circuit detector event is done
by BKSCD[3:0] field in DFSDM_AWSCDyR register.
Short circuit detector cannot be used in case of parallel input data channel selection
(DATMPX[1:0] ≠ 0 in DFSDM_CHCFGyR1 register).
Four break outputs are totally available (shared with the analog watchdog function).
21.3.12

Extremes detector

The purpose of an extremes detector is to collect the minimum and maximum values of final
output data words (peak to peak values).
If the output data word is higher than the value stored in the extremes detector maximum
register (EXMAX[23:0] bits in DFSDMx_EXMAX register), then this register is updated with
the current output data word value and the channel from which the data is stored is in
EXMAXCH[2:0] bits (in DFSDMx_EXMAX register) .
If the output data word is lower than the value stored in the extremes detector minimum
register (EXMIN[23:0] bits in DFSDMx_EXMIN register), then this register is updated with
the current output data word value and the channel from which the data is stored is in
EXMINCH[2:0] bits (in DFSDMx_EXMIN register).
The minimum and maximum register values can be refreshed by software (by reading given
DFSDMx_EXMAX or DFSDMx_EXMIN register). After refresh, the extremes detector
minimum data register DFSDMx_EXMIN is filled with 0x7FFFFF (maximum positive value)
and the extremes detector maximum register DFSDMx_EXMAX is filled with 0x800000
(minimum negative value).
The extremes detector performs a comparison after an offset and a bit shift data correction.
For each extremes detector, the input channels to be considered into computing the
extremes value are selected in EXCH[7:0] bits (in DFSDMx_CR2 register).
21.3.13 Data unit block
The data unit block is the last block of the whole processing path: External Σ∆ modulators -
Serial transceivers - Sinc filter - Integrator - Data unit block.
The output data rate depends on the serial data stream rate, and filter and integrator
settings. The maximum output data rate is:
Datarate samples
Digital filter for sigma delta modulators (DFSDM)
f
DFSDM_CKIN
⁄ --------------------------------------------------------------------------------------------------------- -
s
=
F ⋅ ( I
–
OSR OSR
DocID024597 Rev 3
1 F ) ( F 1 )
+ + +
ORD ORD
...FAST = 0, Sincx filter
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