Table 69. Fmc_Bwtrx Bit Fields; Figure 42. Muxed Read Access Waveforms - ST STM32L4x6 Reference Manual

RM0351
Bit number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
Muxed mode - multiplexed asynchronous access to NOR Flash memory

Table 69. FMC_BWTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x3
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST + 1 HCLK cycles) for
DATAST
write accesses.
Duration of the middle phase of the write access (ADDHLD HCLK
ADDHLD
cycles)
Duration of the first access phase (ADDSET HCLK cycles) for write
ADDSET
accesses. Minimum value for ADDSET is 1.

Figure 42. Muxed read access waveforms

DocID024597 Rev 3
Flexible static memory controller (FSMC)
Value to set
367/1693
399