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Flexible static memory controller (FSMC)
FMC signal name I/O
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
NBL[1:0]
The maximum capacity is 512 Mbits (26 address lines).
14.5.2
Supported memories and transactions
Table 55
transactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and
SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in
this example.
Table 55. NOR Flash/PSRAM: example of supported memories and transactions
Device
NOR Flash
(muxed I/Os
and nonmuxed
I/Os)
352/1693
Table 54. 16-Bit multiplexed I/O PSRAM (continued)
O
Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))
O
O
O
I
O
Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)
below shows an example of the supported devices, access modes and
Mode
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
page
Synchronous
Synchronous
Synchronous
DocID024597 Rev 3
Output enable
Write enable
Address valid PSRAM input (memory signal name: NADV)
PSRAM wait input signal to the FMC
AHB
Memory
R/W
data
data size
size
R
8
16
W
8
16
R
16
16
W
16
16
R
32
16
W
32
16
R
-
16
R
8
16
R
16
16
R
32
16
Function
Allowed/
not
Comments
allowed
Y
N
Y
Y
Y
Split into 2 FMC accesses
Y
Split into 2 FMC accesses
N
Mode is not supported
N
Y
Y
RM0351
-
-
-
-
-
-
-
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