Table 125. Dfsdm Interrupt Requests - ST STM32L4x6 Reference Manual

Digital filter for sigma delta modulators (DFSDM)
–
–
–
–
–
• Short-circuit detector interrupt:
–
–
–
–
•
Channel clock absence interrupt:
–
–
–
–
Interrupt event
End of injected conversion
End of regular conversion
Injected data overrun
Regular data overrun
Analog watchdog
short-circuit detector
Channel clock absence
628/1693
occurred when converted data (output data or data from analog watchdog filter -
according to AWFSEL bit setting in DFSDMx_CR1 register) crosses over/under
high/low thresholds in DFSDMx_AWHTR / DFSDMx_AWLTR registers
enabled by AWDIE bit in DFSDMx_CR2 register (on selected channels
AWDCH[7:0])
indicated in AWDF bit in DFSDMx_ISR register
separate indication of high or low analog watchdog threshold error by AWHTF[7:0]
and AWLTF[7:0] fields in DFSDMx_AWSR register
cleared by writing '1' into corresponding CLRAWHTF[7:0] or CLRAWLTF[7:0] bits
in DFSDMx_AWCFR register
occurred when the number of stable data crosses over thresholds in
DFSDM_AWSCDyR register
enabled by SCDIE bit in DFSDMx_CR2 register (on channel selected by SCDEN
bi tin DFSDM_CHCFGyR1 register)
indicated in SCDF[7:0] bits in DFSDMx_ISR register (which also reports the
channel on which the short-circuit detector event occurred)
cleared by writing '1' into the corresponding CLRSCDF[7:0] bit in DFSDMx_ICR
register
occurred when there is clock absence on DFSDM_CKINy pin (see
detection in Section 21.3.4: Serial channel
enabled by CKABIE bit in DFSDMx_CR2 register (on channels selected by
CKABEN bit in DFSDM_CHCFGyR1 register)
indicated in CKABF[y] bit in DFSDMx_ISR register
cleared by writing '1' into CLRCKABF[y] bit in DFSDMx_ICR register

Table 125. DFSDM interrupt requests

Event flag
JEOCF
REOCF
JOVRF
ROVRF
AWDF,
AWHTF[7:0],
AWLTF[7:0]
SCDF[7:0]
CKABF[7:0]
DocID024597 Rev 3
transceivers)
Event/Interrupt clearing
method
reading DFSDMx_JDATAR
reading DFSDMx_RDATAR
writing CLRJOVRF = 1
writing CLRROVRF = 1
writing CLRAWHTF[7:0] = 1
writing CLRAWLTF[7:0] = 1
writing CLRSCDF[7:0] = 1
writing CLRCKABF[7:0] = 1
RM0351
Clock absence
Interrupt enable
control bit
JEOCIE
REOCIE
JOVRIE
ROVRIE
AWDIE,
(AWDCH[7:0])
SCDIE,
(SCDEN)
CKABIE,
(CKABEN)