Ahb3 Peripheral Reset Register (Rcc_Ahb3Rstr) - ST STM32L4x6 Reference Manual

Table of Contents

Advertisement

Reset and clock control (RCC)
Bit 7 GPIOHRST: IO port H reset
Bit 6 GPIOGRST: IO port G reset
Bit 5 GPIOFRST: IO port F reset
Bit 4 GPIOERST: IO port E reset
Bit 3 GPIODRST: IO port D reset
Bit 2 GPIOCRST: IO port C reset
Bit 1 GPIOBRST: IO port B reset
Bit 0 GPIOARST: IO port A reset
6.4.12

AHB3 peripheral reset register (RCC_AHB3RSTR)

Address offset: 0x30
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
218/1693
Set and cleared by software.
0: No effect
1: Reset IO port H
Set and cleared by software.
0: No effect
1: Reset IO port G
Set and cleared by software.
0: No effect
1: Reset IO port F
Set and cleared by software.
0: No effect
1: Reset IO port E
Set and cleared by software.
0: No effect
1: Reset IO port D
Set and cleared by software.
0: No effect
1: Reset IO port C
Set and cleared by software.
0: No effect
1: Reset IO port B
Set and cleared by software.
0: No effect
1: Reset IO port A
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
QSPI
Res.
Res.
RST
rw
DocID024597 Rev 3
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
RM0351
17
16
Res.
Res.
1
0
FMC
Res.
RST
rw

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the STM32L4x6 and is the answer not in the manual?

Questions and answers

Table of Contents

Save PDF