Clock Configuration Register (Rcc_Cfgr) - ST STM32L4x6 Reference Manual

Reset and clock control (RCC)
6.4.3

Clock configuration register (RCC_CFGR)

Address offset: 0x08
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during clock source switch.
From 0 to 15 wait states inserted if the access occurs when the APB or AHB prescalers
values update is on going.
31 30 29
Res. MCOPRE[2:0]
rw rw
15 14 13
STOP
Res. PPRE2[2:0]
WUCK
rw rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:28 MCOPRE[2:0]: Microcontroller clock output prescaler
Bit 27 Reserved, must be kept at reset value.
Bits 26:24 MCOSEL[2:0]: Microcontroller clock output
Note: This clock output may have some truncated cycles at startup or during MCO clock
Bits 23:16 Reserved, must be kept at reset value.
200/1693
28 27 26 25
Res. MCOSEL[2:0]
rw rw rw
12 11 10 9
PPRE1[2:0]
rw rw rw rw
These bits are set and cleared by software.
It is highly recommended to change this prescaler before MCO output is enabled.
000: MCO is divided by 1
001: MCO is divided by 2
010: MCO is divided by 4
011: MCO is divided by 8
100: MCO is divided by 16
Others: not allowed
Set and cleared by software.
000: MCO output disabled, no clock on MCO
001: SYSCLK system clock selected
010: MSI clock selected.
011: HSI16 clock selected.
100: HSE clock selected
101: Main PLL clock selected
110: LSI clock selected
111: LSE clock selected
source switching.
24 23 22
Res. Res.
rw
8 7 6
HPRE[3:0]
rw rw rw
DocID024597 Rev 3
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
SWS[1:0]
rw rw r r
RM0351
17 16
Res. Res.
1 0
SW[1:0]
rw rw