Lptim Interrupt Enable Register (Lptimx_Ier) - ST STM32L4x6 Reference Manual

RM0351
30.7.3

LPTIM interrupt enable register (LPTIMx_IER)

Address offset: 0x08
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:7 Reserved, must be kept at reset value.
Bit 6 DOWNIE: Direction change to down Interrupt Enable
0: DOWN interrupt disabled
1: DOWN interrupt enabled
Bit 5 UPIE: Direction change to UP Interrupt Enable
0: UP interrupt disabled
1: UP interrupt enabled
Bit 4 ARROKIE: Autoreload register update OK Interrupt Enable
0: ARROK interrupt disabled
1: ARROK interrupt enabled
Bit 3 CMPOKIE: Compare register update OK Interrupt Enable
0: CMPOK interrupt disabled
1: CMPOK interrupt enabled
Bit 2 EXTTRIGIE: External trigger valid edge Interrupt Enable
0: EXTTRIG interrupt disabled
1: EXTTRIG interrupt enabled
Bit 1 ARRMIE: Autoreload match Interrupt Enable
0: ARRM interrupt disabled
1: ARRM interrupt enabled
Bit 0 CMPMIE: Compare match Interrupt Enable
0: CMPM interrupt disabled
1: CMPM interrupt enabled
Caution: The LPTIMx_IER register must only be modified when the LPTIM is disabled (ENABLE bit is reset to '0')
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
DocID024597 Rev 3
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
DOWNI
Res. Res. UPIE
E
rw rw
Low-power timer (LPTIM)
20 19 18 17
Res. Res. Res. Res.
4 3 2
ARRO CMPO EXTTR ARRMI
KIE KIE IGIE E
rw rw rw rw
16
Res.
1 0
CMPMI
E
rw
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