Bit Banding - ST STM32L4x6 Reference Manual

RM0351
Table 1. STM32L4x6 memory map and peripheral register boundary addresses (continued)
Bus Boundary address
0x4000 5000 - 0x4000 53FF
0x4000 4C00 - 0x4000 4FFF
0x4000 4800 - 0x4000 4BFF
0x4000 4400 - 0x4000 47FF
0x4000 4000 - 0x4000 43FF
0x4000 3C00 - 0x4000 3FFF
0x4000 3800 - 0x4000 3BFF
0x4000 3400 - 0x4000 37FF
0x4000 3000 - 0x4000 33FF
0x4000 2C00 - 0x4000 2FFF
APB1
0x4000 2800 - 0x4000 2BFF
0x4000 2400 - 0x4000 27FF
0x4000 1800 - 0x4000 2400
0x4000 1400 - 0x4000 17FF
0x4000 1000 - 0x4000 13FF
0x4000 0C00- 0x4000 0FFF
0x4000 0800 - 0x4000 0BFF
0x4000 0400 - 0x4000 07FF
0x4000 0000 - 0x4000 03FF
2.3

Bit banding

The Cortex
in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the
Size (bytes)
®
-M4 memory map includes two bit-band regions. These regions map each word
DocID024597 Rev 3
Peripheral
1 KB UART5
1 KB UART4
1 KB USART3
1 KB USART2
1 KB Reserved
1 KB SPI3
1 KB SPI2
1 KB Reserved
1 KB IWDG
1 KB WWDG
1 KB RTC
1 KB LCD
3 KB Reserved
1 KB TIM7
1 KB TIM6
1 KB TIM5
1 KB TIM4
1 KB TIM3
1 KB TIM2
Peripheral register map
Section 36.8.12: USART
register map
Section 36.8.12: USART
register map
Section 36.8.12: USART
register map
Section 36.8.12: USART
register map
-
Section 38.6.8: SPI register map
Section 38.6.8: SPI register map
-
Section 32.4.6: IWDG register
map
Section 33.4.4: WWDG register
map
Section 34.6.21: RTC register
map
Section 22.6.6: LCD register
map
-
Section 29.4.9: TIM6/TIM7
register map
Section 29.4.9: TIM6/TIM7
register map
Section 27.4.23: TIMx register
map
Section 27.4.23: TIMx register
map
Section 27.4.23: TIMx register
map
Section 27.4.23: TIMx register
map
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