Table 127. Dfsdmx Register Map And Reset Values - ST STM32L4x6 Reference Manual

Digital filter for sigma delta modulators (DFSDM)
The following table summarizes the DFSDMx registers.
Offset Register
DFSDM0_
CR1
0x100
reset value
DFSDM0_
CR2
0x104
reset value
DFSDM0_
ISR
0x108
reset value 0
DFSDM0_
ICR
0x10C
reset value 0
DFSDM0_
JCHGR
0x110
reset value
DFSDM0_
FCR
0x114
reset value 0
DFSDM0_
JDATAR
0x118
reset value 0
DFSDM0_
RDATAR
0x11C
reset value 0
DFSDM0_
AWHTR
0x120
reset value 0
DFSDM0_
AWLTR
0x124
reset value 0
DFSDM0_
AWSR
0x128
reset value
DFSDM0_
AWCFR
0x12C
reset value
652/1693

Table 127. DFSDMx register map and reset values

RCH[2:0]
0 0 0 0 0
0 0
SCDF[7:0]
0 0 0 0 0 0 0 1 1
CLRSCDF[7:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
DocID024597 Rev 3
0 0 0 0 0
AWDCH[7:0]
0 0 0 0 0 0 0 0
CKABF[7:0]
1 1 1 1 1 1 0
CLRCKABF[7:0]
0 0 0 0 0 0
FOSR[9:0]
0 0 0 0 0 0
JDATA[23:0]
0 0 0 0 0 0 0 0
RDATA[23:0]
0 0 0 0 0 0 0 0
AWHT[23:0]
0 0 0 0 0 0 0 0
AWLT[23:0]
0 0 0 0 0 0 0 0
0 0
0 0
0 0 0 0
EXCH[7:0]
0 0 0 0 0 0 0
0
0 0
0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
AWHTF[7:0]
0 0 0 0 0 0 0 0
CLRAWHTF[7:0] CLRAWLTF[7:0]
0 0 0 0 0 0 0 0
RM0351
0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0
0 0
JCHG[7:0]
0 0 0 0 0 1
IOSR[7:0]
0 0 0 0 0 0
0 0 0
RDATA
CH[2:0]
0 0 0 0
BKAWH[3:0]
0 0 0 0
BKAWL[3:0]
0 0 0 0
AWLTF[7:0]
0 0 0 0 0 0
0 0 0 0 0 0