ST STM32L4x6 Reference Manual page 318

Direct memory access controller (DMA)
Offset Register
DMA_CPAR4
0x4C
Reset value 0
DMA_CMAR4
0x50
Reset value 0
0x54
DMA_CCR5
0x58
Reset value
DMA_CNDTR5
0x5C
Reset value
DMA_CPAR5
0x60
Reset value 0
DMA_CMAR5
0x64
Reset value 0
0x068
DMA_CCR6
0x06C
Reset value
DMA_CNDTR6
0x070
Reset value
DMA_CPAR6
0x074
Reset value 0
DMA_CMAR6
0x078
Reset value 0
0x07C
DMA_CCR7
0x080
Reset value
DMA_CNDTR7
0x084
Reset value
DMA_CPAR7
0x088
Reset value 0
DMA_CMAR7
0x08C
Reset value 0
0x090
DMA_CSELR
0x0A8
Reset value
Refer to
318/1693
Table 41. DMA register map and reset values (continued)
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
C7S[3:0]
0 0 0 0 0
Section 2.2.2 on page 67
PA[31:0]
0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0
Reserved
0
PA[31:0]
0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0
Reserved
0
PA[31:0]
0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0
Reserved
0
PA[31:0]
0 0 0 0 0 0 0 0
MA[31:0]
0 0 0 0 0 0 0 0
Reserved
C6S[3:0] C5S[3:0]
0 0 0 0 0 0 0 0
for the register boundary addresses.
DocID024597 Rev 3
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PL
[1:0]
0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PL
[1:0]
0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
PL
[1:0]
0 0 0 0 0 0 0 0
NDT[15:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
C4S[3:0] C3S[3:0] C2S[3:0]
0 0 0 0 0 0 0 0
RM0351
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
C1S[3:0]
0 0 0 0 0 0 0