Figure 282. Combined Pwm Mode On Channels 1 And 3; Clearing The Ocxref Signal On An External Event - ST STM32L4x6 Reference Manual

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
When a given channel is used as combined PWM channel, its secondary channel must be
configured in the opposite PWM mode (for instance, one in Combined PWM mode 1 and the
other in Combined PWM mode 2).
Note: The OCxM[3:0] bit field is split into two parts for compatibility reasons, the most significant
bit is not contiguous with the 3 least significant ones.
Figure 282
mode, obtained with the following configuration:
•
Channel 1 is configured in Combined PWM mode 2,
• Channel 2 is configured in PWM mode 1,
•
Channel 3 is configured in Combined PWM mode 2,
• Channel 4 is configured in PWM mode 1
27.3.12

Clearing the OCxREF signal on an external event

The OCxREF signal of a given channel can be cleared when a high level is applied on the
OCREF_CLR_INPUT (OCxCE enable bit in the corresponding TIMx_CCMRx register set to
1). OCxREF remains low until the next update event (UEV) occurs. This function can only
be used in Output compare and PWM modes. It does not work in Forced mode.
OCREF_CLR_INPUT can be selected between the OCREF_CLR input and ETRF (ETR
after the filter) by configuring the OCCS bit in the TIMx_SMCR register.
When ETRF is chosen, ETR must be configured as follows:
886/1693
shows an example of signals that can be generated using Asymmetric PWM

Figure 282. Combined PWM mode on channels 1 and 3

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