Figure 66. Enabling / Disabling The Adc; Constraints When Writing The Adc Control Bits - ST STM32L4x6 Reference Manual

RM0351
16.3.10

Constraints when writing the ADC control bits

The software is allowed to write the RCC control bits to configure and enable the ADC clock
(refer to RCC Section), the control bits DIFSEL in the ADCx_DIFSEL register and the
control bits ADCAL and ADEN in the ADCx_CR register, only if the ADC is disabled (ADEN
must be equal to 0).
The software is then allowed to write the control bits ADSTART, JADSTART and ADDIS of
the ADCx_CR register only if the ADC is enabled and there is no pending request to disable
the ADC (ADEN must be equal to 1 and ADDIS to 0).
For all the other control bits of the ADCx_CFGR, ADCx_SMPRx, ADCx_TRx, ADCx_SQRx,
ADCx_JDRy, ADCx_OFRy, ADCx_OFCHR and ADCx_IER registers:
•
For control bits related to configuration of regular conversions, the software is allowed
to write them only if the ADC is enabled (ADEN=1) and if there is no regular conversion
ongoing (ADSTART must be equal to 0).
•
For control bits related to configuration of injected conversions, the software is allowed
to write them only if the ADC is enabled (ADEN=1) and if there is no injected
conversion ongoing (JADSTART must be equal to 0).
The software is allowed to write the control bits ADSTP or JADSTP of the ADCx_CR
register only if the ADC is enabled and eventually converting and if there is no pending
request to disable the ADC (ADSTART or JADSTART must be equal to 1 and ADDIS to 0).
The software can write the register ADCx_JSQR at any time, when the ADC is enabled
(ADEN=1).
Note: There is no hardware protection to prevent these forbidden write accesses and ADC
behavior may become in an unknown state. To recover from this situation, the ADC must be
disabled (clear ADEN=0 as well as all the bits of ADCx_CR register).

Figure 66. Enabling / Disabling the ADC

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Analog-to-digital converters (ADC)
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