ST STM32L4x6 Reference Manual page 649

RM0351
Table 126. DFSDM register map and reset values (continued)
Offset Register
DFSDM_
CHCFG2R1
0x40
reset value
DFSDM_
CHCFG2R2
0x44
reset value 0
DFSDM_
AWSCD2R
0x48
reset value
DFSDM_
CHWDAT2R
0x4C
reset value
DFSDM_
CHDATIN2R
0x50
reset value 0
0x54 -
Reserved
0x5C
DFSDM_
CHCFG3R1
0x60
reset value
DFSDM_
CHCFG3R2
0x64
reset value 0
DFSDM_
AWSCD3R
0x68
reset value
DFSDM_
CHWDAT3R
0x6C
reset value
DFSDM_
CHDATIN3R
0x70
reset value 0
0x74 -
Reserved
0x7C
DFSDM_
CHCFG4R1
0x80
reset value
0 0 0 0 0 0 0 0 0
0 0
INDAT1[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0
INDAT1[15:0]
0 0 0 0 0 0 0 0 0
DocID024597 Rev 3
Digital filter for sigma delta modulators (DFSDM)
0 0
OFFSET[23:0]
0 0 0 0 0 0 0 0
AWFOSR[4:0] BKSCD[3:0]
0 0 0 0 0 0 0
0 0
0 0 0 0 0 0 0 0
0 0
OFFSET[23:0]
0 0 0 0 0 0 0 0
AWFOSR[4:0] BKSCD[3:0]
0 0 0 0 0 0 0
0 0
0 0 0 0 0 0 0 0
0 0
0 0 0 0 0 0
DTRBS[4:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0
WDATA[15:0]
0 0 0 0 0 0 0 0 0
INDAT0[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
DTRBS[4:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0
WDATA[15:0]
0 0 0 0 0 0 0 0 0
INDAT0[15:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0
0 0
SCDT[7:0]
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0
0 0
SCDT[7:0]
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0
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