Table 58. Fmc_Bcrx Bit Fields; Table 59. Fmc_Btrx Bit Fields - ST STM32L4x6 Reference Manual

Flexible static memory controller (FSMC)
The differences compared with Mode1 are the toggling of NOE and the independent read
and write timings.
Bit number
31-21
20
19
18:16
15
14
13
12
11
11
9
8
7
6
5-4
3-2
1
0
Bit number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
358/1693

Table 58. FMC_BCRx bit fields

Bit name
Reserved 0x000
CCLKEN As needed
CBURSTRW 0x0 (no effect in asynchronous mode)
CPSIZE 0x0 (no effect in asynchronous mode)
ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
EXTMOD 0x1
WAITEN 0x0 (no effect in asynchronous mode)
WREN As needed
WAITCFG Don't care
Reserved 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
FACCEN Don't care
MWID As needed
MTYP As needed, exclude 0x2 (NOR Flash memory)
MUXEN 0x0
MBKEN 0x1

Table 59. FMC_BTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST HCLK cycles) for read
DATAST
accesses.
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses.
ADDSET
Minimum value for ADDSET is 0.
DocID024597 Rev 3
Value to set
Value to set
RM0351