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STM32F446 Series
ST STM32F446 Series Development Board Manuals
Manuals and User Guides for ST STM32F446 Series Development Board. We have
2
ST STM32F446 Series Development Board manuals available for free PDF download: Reference Manual, Application Note
ST STM32F446 Series Reference Manual (1328 pages)
advanced Arm-based 32-bit MCUs
Brand:
ST
| Category:
Microcontrollers
| Size: 16 MB
Table of Contents
Table of Contents
2
SYSCFG External Interrupt Configuration Register
4
Documentation Conventions
51
List of Abbreviations for Registers
51
Glossary
52
Peripheral Availability
52
Memory and Bus Architecture
53
System Architecture
53
I-Bus
54
D-Bus
54
S-Bus
54
DMA Memory Bus
54
Figure 1. System Architecture for Stm32F446Xx Devices
54
AHB/APB Bridges (APB)
55
Busmatrix
55
USB OTG HS DMA Bus
55
DMA Peripheral Bus
55
Memory Organization
56
Introduction
56
Memory Map and Register Boundary Addresses
56
Figure 2. Memory Map
56
Table 1. Stm32F446Xx Register Boundary Addresses
57
Embedded SRAM
60
Flash Memory Overview
60
Bit Banding
60
Boot Configuration
61
Table 2. Boot Modes
61
Table 3. Memory Mapping Vs. Boot Mode/Physical Remap in Stm32F446Xx
62
Figure 3. Flash Memory Interface Connection Inside System Architecture
64
Main Features
64
Introduction
64
Embedded Flash Memory Interface
64
Embedded Flash Memory
65
Table 4. Flash Module Organization
65
Read Interface
66
Relation between CPU Clock Frequency and Flash Memory Read Time
66
Table 5. Number of Wait States According to CPU Clock (HCLK) Frequency
66
Adaptive Real-Time Memory Accelerator (ART Accelerator™)
67
Figure 4. Sequential 32-Bit Instruction Execution
68
Erase and Program Operations
69
Unlocking the Flash Control Register
69
Program/Erase Parallelism
70
Erase
70
Table 6. Program/Erase Parallelism
70
Programming
71
Interrupts
72
Option Bytes
72
Description of User Option Bytes
72
Table 7. Flash Interrupt Request
72
Table 8. Option Byte Organization
72
Table 9. Description of the Option Bytes
73
Programming User Option Bytes
74
Read Protection (RDP)
74
Table 10. Access Versus Read Protection Level
76
Write Protections
77
Figure 5. RDP Levels
77
Proprietary Code Readout Protection (PCROP)
78
Figure 6. PCROP Levels
79
One-Time Programmable Bytes
79
Table 11. OTP Area Organization
79
Flash Interface Registers
80
Flash Access Control Register (FLASH_ACR)
80
Flash Key Register (FLASH_KEYR)
81
Flash Option Key Register (FLASH_OPTKEYR)
81
Flash Status Register (FLASH_SR)
82
Flash Control Register (FLASH_CR)
83
Flash Option Control Register (FLASH_OPTCR)
85
Flash Interface Register Map
87
Table 12. Flash Register Map and Reset Value
87
Figure 7. CRC Calculation Unit Block Diagram
88
CRC Functional Description
88
CRC Main Features
88
CRC Introduction
88
CRC Calculation Unit
88
CRC Registers
89
Data Register (CRC_DR)
89
Independent Data Register (CRC_IDR)
90
Control Register (CRC_CR)
90
CRC Register Map
91
Table 13. CRC Calculation Unit Register Map and Reset Values
91
Power Controller (PWR)
92
Power Supplies
92
Figure 8. Power Supply Overview for Stm32F446Xx
92
Independent A/D Converter Supply and Reference Voltage
93
Battery Backup Domain
93
Table 24. RTC_AF1 Pin
93
Figure 9. Backup Domain
95
Voltage Regulator
95
Table 14. Voltage Regulator Configuration Mode Versus Device Operating Mode
96
Power Supply Supervisor
98
Power-On Reset (Por)/Power-Down Reset (PDR)
98
Figure 10. Power-On Reset/Power-Down Reset Waveform
98
Brownout Reset (BOR)
99
Programmable Voltage Detector (PVD)
99
Figure 11. BOR Thresholds
99
Low-Power Modes
100
Figure 12. PVD Thresholds
100
Slowing down System Clocks
101
Peripheral Clock Gating
101
Table 15. Low-Power Mode Summary
101
Sleep Mode
102
Low Power Mode
102
Stop Mode
103
Table 16. Sleep-Now Entry and Exit
103
Table 17. Stop Operating Modes
104
Standby Mode
106
Table 18. Stop Mode Entry and Exit for Stm32F446Xx
106
Table 19. Standby Mode Entry and Exit
107
Programming the RTC Alternate Functions to Wake up the Device from the Stop and Standby Modes
108
Power Control Registers
111
PWR Power Control Register (PWR_CR)
111
PWR Power Control/Status Register (PWR_CSR)
113
PWR Register Map
115
Table 20. PWR - Register Map and Reset Values
115
Power Reset
116
Reset
116
System Reset
116
Reset and Clock Control (RCC)
116
Backup Domain Reset
117
Clocks
117
Figure 13. Simplified Diagram of the Reset Circuit
117
Figure 14. Clock Tree
118
HSE Clock
120
Figure 15. HSE/ LSE Clock Sources (Hardware Configuration)
120
HSI Clock
121
PLL Configuration
121
LSE Clock
122
LSI Clock
122
System Clock (SYSCLK) Selection
122
RTC/AWU Clock
123
Clock Security System (CSS)
123
Watchdog Clock
124
Clock-Out Capability
124
Internal/External Clock Measurement Using TIM5/TIM11
125
Figure 16. Frequency Measurement with TIM5 in Input Capture Mode
125
Figure 17. Frequency Measurement with TIM11 in Input Capture Mode
126
RCC Registers
127
RCC Clock Control Register (RCC_CR)
127
RCC PLL Configuration Register (RCC_PLLCFGR)
129
RCC Clock Configuration Register (RCC_CFGR)
131
RCC Clock Interrupt Register (RCC_CIR)
133
RCC AHB1 Peripheral Reset Register (RCC_AHB1RSTR)
136
RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR)
138
RCC AHB3 Peripheral Reset Register (RCC_AHB3RSTR)
138
RCC APB1 Peripheral Reset Register (RCC_APB1RSTR)
139
RCC APB2 Peripheral Reset Register (RCC_APB2RSTR)
142
RCC AHB1 Peripheral Clock Enable Register (RCC_AHB1ENR)
144
RCC AHB2 Peripheral Clock Enable Register (RCC_AHB2ENR)
145
RCC AHB3 Peripheral Clock Enable Register (RCC_AHB3ENR)
146
RCC APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
146
RCC APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
149
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB1LPENR)
151
RCC AHB2 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB2LPENR)
153
RCC AHB3 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB3LPENR)
154
RCC APB1 Peripheral Clock Enable in Low Power Mode Register (RCC_APB1LPENR)
154
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register (RCC_APB2LPENR)
158
RCC Backup Domain Control Register (RCC_BDCR)
159
RCC Clock Control & Status Register (RCC_CSR)
161
RCC Spread Spectrum Clock Generation Register (RCC_SSCGR)
162
RCC PLLI2S Configuration Register (RCC_PLLI2SCFGR)
163
RCC PLL Configuration Register (RCC_PLLSAICFGR)
166
RCC Dedicated Clock Configuration Register (RCC_DCKCFGR)
167
RCC Clocks Gated Enable Register (CKGATENR)
169
RCC Dedicated Clocks Configuration Register 2 (DCKCFGR2)
170
RCC Register Map
172
Table 21. RCC Register Map and Reset Values
172
General-Purpose I/Os (GPIO)
176
GPIO Introduction
176
GPIO Main Features
176
GPIO Functional Description
176
Table 22. Port Bit Configuration Table
177
Figure 18. Basic Structure of a 5 V Tolerant I/O Port Bit
177
I/O Pin Multiplexer and Mapping
178
General-Purpose I/O (GPIO)
178
Table 23. Flexible SWJ-DP Pin Assignment
179
I/O Port Control Registers
180
Figure 19. Selecting an Alternate Function on Stm32F446Xx
180
I/O Port Data Registers
181
I/O Data Bitwise Handling
181
GPIO Locking Mechanism
181
I/O Alternate Function Input/Output
182
External Interrupt/Wakeup Lines
182
Input Configuration
182
Output Configuration
183
Figure 20. Input Floating/Pull Up/Pull down Configurations
183
Figure 22. Alternate Function Configuration
184
Figure 21. Output Configuration
184
Alternate Function Configuration
184
Analog Configuration
185
Using the OSC32_IN/OSC32_OUT Pins as GPIO PC14/PC15
185
Port Pins
185
Using the OSC_IN/OSC_OUT Pins as GPIO PH0/PH1 Port Pins
185
Figure 23. High Impedance-Analog Configuration
185
Selection of RTC Additional_Af1 and RTC_AF2 Alternate Functions
186
GPIO Registers
187
GPIO Port Mode Register (Gpiox_Moder) (X = A..H
187
Table 25. RTC_AF2 Pin
187
GPIO Port Output Type Register (Gpiox_Otyper) (X = A..H
188
GPIO Port Output Speed Register (Gpiox_Ospeedr) (X = A..H
188
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupdr) (X = A..H
189
GPIO Port Input Data Register (Gpiox_Idr) (X = A..H
189
GPIO Port Configuration Lock Register (Gpiox_Lckr) (X = A..H
190
GPIO Port Bit Set/Reset Register (Gpiox_Bsrr) (X = A..H
190
GPIO Port Output Data Register (Gpiox_Odr) (X = A..H
190
GPIO Alternate Function High Register (Gpiox_Afrh) (X = a
192
GPIO Alternate Function Low Register (Gpiox_Afrl) (X = a
192
GPIO Register Map
193
Table 26. GPIO Register Map and Reset Values
193
System Configuration Controller (SYSCFG)
195
I/O Compensation Cell
195
SYSCFG Registers
195
SYSCFG Memory Remap Register (SYSCFG_MEMRMP)
195
SYSCFG Peripheral Mode Configuration Register (SYSCFG_PMC)
197
SYSCFG External Interrupt Configuration Register 1
197
(Syscfg_Exticr1)
197
SYSCFG External Interrupt Configuration Register 2
198
(Syscfg_Exticr2)
198
(Syscfg_Exticr4)
199
SYSCFG External Interrupt Configuration Register 3
199
(Syscfg_Exticr3)
199
Compensation Cell Control Register (SYSCFG_CMPCR)
200
SYSCFG Configuration Register (SYSCFG_CFGR)
200
SYSCFG Register Maps
202
Table 27. SYSCFG Register Map and Reset Values
202
Direct Memory Access Controller (DMA)
203
DMA Introduction
203
DMA Main Features
203
DMA Functional Description
205
DMA Block Diagram
205
DMA Overview
205
Figure 24. DMA Block Diagram
205
Figure 25. Channel Selection
206
Channel Selection
206
DMA Transactions
206
Table 28. DMA1 Request Mapping
207
Table 29. DMA2 Request Mapping
207
Arbiter
208
DMA Streams
208
Source, Destination and Transfer Modes
208
Table 30. Source and Destination Address
208
Figure 26. Peripheral-To-Memory Mode
209
Figure 27. Memory-To-Peripheral Mode
210
Pointer Incrementation
211
Figure 28. Memory-To-Memory Mode
211
Circular Mode
212
Double-Buffer Mode
212
Table 31. Source and Destination Address Registers in Double-Buffer Mode (DBM = 1)
213
Programmable Data Width, Packing/Unpacking, Endianness
213
Table 32. Packing/Unpacking and Endian Behavior (Bit PINC = MINC = 1)
214
Table 33. Restriction on NDT Versus PSIZE and MSIZE
214
Single and Burst Transfers
215
Fifo
215
Figure 29. FIFO Structure
215
Table 34. FIFO Threshold Configurations
216
DMA Transfer Completion
218
DMA Transfer Suspension
219
Flow Controller
219
Summary of the Possible DMA Configurations
220
Table 35. Possible DMA Configurations
220
Stream Configuration Procedure
221
Error Management
222
Table 36. DMA Interrupt Requests
223
DMA Interrupts
223
DMA Registers
224
DMA Low Interrupt Status Register (DMA_LISR)
224
DMA High Interrupt Status Register (DMA_HISR)
225
DMA Low Interrupt Flag Clear Register (DMA_LIFCR)
226
DMA High Interrupt Flag Clear Register (DMA_HIFCR)
226
DMA Stream X Configuration Register (Dma_Sxcr) (X = 0
227
DMA Stream X Number of Data Register (Dma_Sxndtr) (X = 0
230
DMA Stream X Peripheral Address Register (Dma_Sxpar) (X = 0
231
DMA Stream X Memory 0 Address Register (Dma_Sxm0Ar) (X = 0
231
DMA Stream X Memory 1 Address Register (Dma_Sxm1Ar) (X = 0
232
DMA Stream X FIFO Control Register (Dma_Sxfcr) (X = 0
232
DMA Register Map
234
Table 37. DMA Register Map and Reset Values
234
Interrupt and Exception Vectors
238
Table 38. Vector Table for Stm32F446Xx
238
External Interrupt/Event Controller (EXTI)
238
Interrupts and Events
238
Systick Calibration Value Register
238
NVIC Features
238
Nested Vectored Interrupt Controller (NVIC)
238
EXTI Main Features
242
EXTI Block Diagram
243
Wakeup Event Management
243
Functional Description
243
Figure 30. External Interrupt/Event Controller Block Diagram
243
External Interrupt/Event Line Mapping
245
Figure 31. External Interrupt/Event GPIO Mapping
245
Event Mask Register (EXTI_EMR)
246
EXTI Registers
246
Interrupt Mask Register (EXTI_IMR)
246
Rising Trigger Selection Register (EXTI_RTSR)
247
Falling Trigger Selection Register (EXTI_FTSR)
247
Software Interrupt Event Register (EXTI_SWIER)
248
Pending Register (EXTI_PR)
248
EXTI Register Map
249
Table 39. External Interrupt/Event Controller Register Map and Reset Values
249
Flexible Memory Controller (FMC)
250
FMC Main Features
250
FMC Block Diagram
251
Figure 32. FMC Block Diagram
251
AHB Interface
252
Supported Memories and Transactions
252
Figure 33. FMC Memory Banks
254
External Device Address Mapping
254
NAND Flash Memory Address Mapping
255
Table 40. NOR/PSRAM Bank Selection
255
Table 41. NOR/PSRAM External Memory Address
255
Table 42. NAND Memory Mapping and Timing Registers
255
NOR/PSRAM Address Mapping
255
SDRAM Address Mapping
256
Table 43. NAND Bank Selection
256
Table 44. SDRAM Bank Selection
256
Table 45. SDRAM Address Mapping
256
Table 46. SDRAM Address Mapping with 8-Bit Data Bus Width
257
NOR Flash/Psram Controller
258
Table 47. SDRAM Address Mapping with 16-Bit Data Bus Width
258
Table 48. Programmable NOR/PSRAM Access Parameters
259
Table 50. 16-Bit Multiplexed I/O nor Flash Memory
260
External Memory Interface Signals
260
Table 49. Non-Multiplexed I/O nor Flash Memory
260
Supported Memories and Transactions
261
Table 51. Non-Multiplexed I/Os PSRAM/SRAM
261
Table 52. 16-Bit Multiplexed I/O PSRAM
261
Table 53. nor Flash/Psram: Example of Supported Memories and Transactions
262
General Timing Rules
263
NOR Flash/Psram Controller Asynchronous Transactions
263
Figure 34. Mode1 Read Access Waveforms
264
Figure 35. Mode1 Write Access Waveforms
264
Table 54. Fmc_Bcrx Bit Fields
265
Table 55. Fmc_Btrx Bit Fields
265
Figure 36. Modea Read Access Waveforms
266
Figure 37. Modea Write Access Waveforms
266
Table 56. Fmc_Bcrx Bit Fields
267
Table 57. Fmc_Btrx Bit Fields
267
Table 58. Fmc_Bwtrx Bit Fields
268
Figure 38. Mode2 and Mode B Read Access Waveforms
268
Figure 39. Mode2 Write Access Waveforms
269
Figure 40. Modeb Write Access Waveforms
269
Table 59. Fmc_Bcrx Bit Fields
270
Table 60. Fmc_Btrx Bit Fields
270
Table 61. Fmc_Bwtrx Bit Fields
271
Figure 41. Modec Read Access Waveforms
271
Table 62. Fmc_Bcrx Bit Fields
272
Figure 42. Modec Write Access Waveforms
272
Table 63. Fmc_Btrx Bit Fields
273
Table 64. Fmc_Bwtrx Bit Fields
273
Figure 43. Moded Read Access Waveforms
274
Figure 44. Moded Write Access Waveforms
274
Table 65. Fmc_Bcrx Bit Fields
275
Table 66. Fmc_Btrx Bit Fields
275
Table 67. Fmc_Bwtrx Bit Fields
276
Figure 45. Muxed Read Access Waveforms
276
Table 68. Fmc_Bcrx Bit Fields
277
Figure 46. Muxed Write Access Waveforms
277
Table 69. Fmc_Btrx Bit Fields
278
Figure 47. Asynchronous Wait During a Read Access Waveforms
279
Synchronous Transactions
280
Figure 48. Asynchronous Wait During a Write Access Waveforms
280
Figure 49. Wait Configuration Waveforms
282
Figure 50. Synchronous Multiplexed Read Mode Waveforms - NOR, PSRAM (CRAM)
283
Table 70. Fmc_Bcrx Bit Fields
283
Table 71. Fmc_Btrx Bit Fields
284
Table 72. Fmc_Bcrx Bit Fields
285
Figure 51. Synchronous Multiplexed Write Mode Waveforms - PSRAM (CRAM)
285
Table 73. Fmc_Btrx Bit Fields
286
NOR/PSRAM Controller Registers
287
NAND Flash Controller
294
External Memory Interface Signals
294
Table 74. Programmable NAND Flash Access Parameters
294
Table 75. 8-Bit NAND Flash
294
Table 76. 16-Bit NAND Flash
295
NAND Flash Supported Memories and Transactions
296
Timing Diagrams for NAND Flash Memory
296
Table 77. Supported Memories and Transactions
296
Figure 52. NAND Flash Controller Waveforms for Common Memory Access
297
NAND Flash Operations
297
NAND Flash Prewait Functionality
298
Figure 53. Access to Non 'CE Don't Care' NAND-Flash
298
Computation of the Error Correction Code (ECC) in NAND Flash Memory
299
NAND Flash Controller Registers
300
Table 78. ECC Result Relevant Bits
305
SDRAM Controller
306
SDRAM Controller Main Features
306
SDRAM External Memory Interface Signals
306
Table 79. SDRAM Signals
306
SDRAM Controller Functional Description
307
Figure 54. Burst Write SDRAM Access Waveforms
308
Figure 55. Burst Read SDRAM Access
309
Figure 56. Logic Diagram of Read Access with RBURST Bit Set (CAS=1, RPIPE=0)
310
Figure 57. Read Access Crossing Row Boundary
312
Figure 58. Write Access Crossing Row Boundary
312
Low-Power Modes
313
Figure 59. Self-Refresh Mode
314
SDRAM Controller Registers
315
Figure 60. Power-Down Mode
315
FMC Register Map
323
Table 80. FMC Register Map
323
Quad-SPI Interface (QUADSPI)
325
Introduction
325
QUADSPI Main Features
325
QUADSPI Functional Description
325
QUADSPI Block Diagram
325
Figure 61. QUADSPI Block Diagram When Dual-Flash Mode Is Disabled
325
Figure 62. QUADSPI Block Diagram When Dual-Flash Mode Is Enabled
326
Table 81. QUADSPI Pins
326
QUADSPI Pins
326
QUADSPI Command Sequence
327
Figure 63. an Example of a Read Command in Quad Mode
327
QUADSPI Signal Interface Protocol Modes
329
Figure 64. an Example of a DDR Command in Quad Mode
330
QUADSPI Indirect Mode
331
QUADSPI Status Flag Polling Mode
333
QUADSPI Memory-Mapped Mode
333
QUADSPI Flash Memory Configuration
334
QUADSPI Delayed Data Sampling
334
QUADSPI Configuration
334
QUADSPI Usage
335
QUADSPI Error Management
337
Sending the Instruction Only Once
337
QUADSPI Busy Bit and Abort Functionality
338
Ncs Behavior
338
Figure 65. Ncs When CKMODE = 0 (T = CLK Period)
338
Figure 66. Ncs When CKMODE = 1 in SDR Mode (T = CLK Period)
338
Figure 67. Ncs When CKMODE = 1 in DDR Mode (T = CLK Period)
339
Figure 68. Ncs When CKMODE = 1 with an Abort (T = CLK Period)
339
QUADSPI Interrupts
340
Table 82. QUADSPI Interrupt Requests
340
QUADSPI Registers
341
QUADSPI Control Register (QUADSPI_CR)
341
QUADSPI Device Configuration Register (QUADSPI_DCR)
344
QUADSPI Status Register (QUADSPI_SR)
345
QUADSPI Flag Clear Register (QUADSPI_FCR)
346
QUADSPI Data Length Register (QUADSPI_DLR)
346
QUADSPI Communication Configuration Register (QUADSPI_CCR)
347
QUADSPI Address Register (QUADSPI_AR)
349
QUADSPI Alternate Bytes Registers (QUADSPI_ABR)
350
QUADSPI Data Register (QUADSPI_DR)
350
QUADSPI Polling Status Mask Register (QUADSPI
351
QUADSPI Polling Status Match Register (QUADSPI
351
QUADSPI Polling Interval Register (QUADSPI
352
QUADSPI Low-Power Timeout Register (QUADSPI_LPTR)
352
QUADSPI Register Map
353
Table 83. QUADSPI Register Map and Reset Values
353
Analog-To-Digital Converter (ADC)
354
ADC Introduction
354
ADC Main Features
354
ADC Functional Description
354
Figure 69. Single ADC Block Diagram
355
ADC On-Off Control
356
Table 84. ADC Pins
356
ADC1/2 and ADC3 Connectivity
357
Figure 70. ADC1 Connectivity
357
Figure 71. ADC2 Connectivity
358
Figure 72. ADC3 Connectivity
359
ADC Clock
360
Channel Selection
360
Single Conversion Mode
361
Continuous Conversion Mode
361
Timing Diagram
361
Analog Watchdog
362
Table 85. Analog Watchdog Channel Selection
362
Figure 73. Timing Diagram
362
Figure 74. Analog Watchdog's Guarded Area
362
Injected Channel Management
363
Scan Mode
363
Figure 75. Injected Conversion Latency
364
Discontinuous Mode
364
Data Alignment
365
Channel-Wise Programmable Sampling Time
366
Figure 76. Right Alignment of 12-Bit Data
366
Figure 77. Left Alignment of 12-Bit Data
366
Figure 78. Left Alignment of 6-Bit Data
366
Conversion on External Trigger and Trigger Polarity
367
Table 86. Configuring the Trigger Polarity
367
Table 87. External Trigger for Regular Channels
367
Fast Conversion Mode
368
Table 88. External Trigger for Injected Channels
368
Managing a Sequence of Conversions Without Using the DMA
369
Data Management
369
Using the DMA
369
Conversions Without DMA and Without Overrun Detection
370
Multi ADC Mode
370
Figure 79. Multi ADC Block Diagram (1)
371
Injected Simultaneous Mode
373
Regular Simultaneous Mode
374
Figure 80. Injected Simultaneous Mode on 4 Channels: Dual ADC Mode
374
Figure 81. Injected Simultaneous Mode on 4 Channels: Triple ADC Mode
374
Interleaved Mode
375
Figure 82. Regular Simultaneous Mode on 16 Channels: Dual ADC Mode
375
Figure 83. Regular Simultaneous Mode on 16 Channels: Triple ADC Mode
375
Figure 84. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Dual ADC Mode
376
Figure 85. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Triple ADC Mode
377
Alternate Trigger Mode
377
Figure 86. Alternate Trigger: Injected Group of each ADC
378
Figure 87. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Mode
378
Combined Regular/Injected Simultaneous Mode
379
Combined Regular Simultaneous + Alternate Trigger Mode
379
Figure 88. Alternate Trigger: Injected Group of each ADC
379
Temperature Sensor
380
Figure 89. Alternate + Regular Simultaneous
380
Figure 90. Case of Trigger Occurring During Injected Conversion
380
Figure 91. Temperature Sensor and VREFINT Channel Block Diagram
381
Battery Charge Monitoring
382
ADC Interrupts
382
Table 89. ADC Interrupts
382
ADC Status Register (ADC_SR)
383
ADC Registers
383
ADC Control Register 1 (ADC_CR1)
384
ADC Control Register 2 (ADC_CR2)
386
ADC Sample Time Register 1 (ADC_SMPR1)
388
ADC Sample Time Register 2 (ADC_SMPR2)
388
ADC Injected Channel Data Offset Register X (Adc_Jofrx) (X=1
389
ADC Watchdog Higher Threshold Register (ADC_HTR)
389
ADC Watchdog Lower Threshold Register (ADC_LTR)
390
ADC Regular Sequence Register 1 (ADC_SQR1)
390
ADC Regular Sequence Register 2 (ADC_SQR2)
391
ADC Regular Sequence Register 3 (ADC_SQR3)
392
ADC Injected Sequence Register (ADC_JSQR)
393
ADC Injected Data Register X (Adc_Jdrx) (X= 1
393
ADC Regular Data Register (ADC_DR)
394
ADC Common Status Register (ADC_CSR)
394
ADC Common Control Register (ADC_CCR)
395
13.13.17 ADC Common Regular Data Register for Dual and Triple Modes
398
Table 91. ADC Register Map and Reset Values for each ADC
398
(Adc_Cdr)
398
13.13.18 ADC Register Map
398
Table 90. ADC Global Register Map
398
Table 92. ADC Register Map and Reset Values (Common ADC Registers)
400
Digital-To-Analog Converter (DAC)
401
DAC Introduction
401
DAC Main Features
401
DAC Functional Description
402
DAC Channel Enable
402
Table 93. DAC Pins
402
Figure 92. DAC Channel Block Diagram
402
Figure 93. DAC Output Buffer Connection
403
DAC Data Format
403
DAC Output Buffer Enable
403
Figure 94. Data Registers in Single DAC Channel Mode
404
Figure 95. Data Registers in Dual DAC Channel Mode
404
DAC Conversion
404
DAC Output Voltage
405
DAC Trigger Selection
405
Table 94. External Triggers
405
Figure 96. Timing Diagram for Conversion with Trigger Disabled TEN = 0
405
DMA Request
406
Noise Generation
406
Triangle-Wave Generation
407
Figure 97. DAC LFSR Register Calculation Algorithm
407
Figure 98. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
407
Figure 100. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
408
Dual DAC Channel Conversion
408
Figure 99. DAC Triangle Wave Generation
408
Independent Trigger Without Wave Generation
409
Independent Trigger with Different LFSR Generation
409
Independent Trigger with Single LFSR Generation
409
DAC_DHR12LD or DAC_DHR8RD)
410
Independent Trigger with Different Triangle Generation
410
Independent Trigger with Single Triangle Generation
410
Load the Dual DAC Channel Data into the Desired DHR Register
410
Set the Two DAC Channel Trigger Enable Bits TEN1 and TEN2
410
Simultaneous Software Start
410
TSEL2[2:0] Bits
410
Simultaneous Trigger with Different LFSR Generation
411
Simultaneous Trigger with Single LFSR Generation
411
Simultaneous Trigger Without Wave Generation
411
DAC_DHR12LD or DAC_DHR8RD)
412
Load the Dual DAC Channel Data into the Desired DHR Register
412
MAMP2[3:0], Is Added to the DHR2 Register and the Sum Is Transferred into DAC_DOR2
412
Simultaneous Trigger with Different Triangle Generation
412
Simultaneous Trigger with Single Triangle Generation
412
DAC Control Register (DAC_CR)
413
DAC Registers
413
DAC Channel1 12-Bit Right-Aligned Data Holding Register (DAC_DHR12R1)
416
DAC Software Trigger Register (DAC_SWTRIGR)
416
(Dac_Dhr12L1)
417
DAC Channel1 12-Bit Left Aligned Data Holding Register
417
DAC Channel1 8-Bit Right Aligned Data Holding Register (DAC_DHR8R1)
417
(Dac_Dhr12L2)
418
DAC Channel2 12-Bit Left Aligned Data Holding Register
418
DAC Channel2 12-Bit Right Aligned Data Holding Register (DAC_DHR12R2)
418
DAC Channel2 8-Bit Right-Aligned Data Holding Register (DAC_DHR8R2)
418
(Dac_Dhr12Ld)
419
DUAL DAC 12-Bit Left Aligned Data Holding Register
419
Dual DAC 12-Bit Right-Aligned Data Holding Register (DAC_DHR12RD)
419
(Dac_Dhr8Rd)
420
DAC Channel1 Data Output Register (DAC_DOR1)
420
DAC Channel2 Data Output Register (DAC_DOR2)
420
DUAL DAC 8-Bit Right Aligned Data Holding Register
420
DAC Status Register (DAC_SR)
421
DAC Register Map
422
Table 95. DAC Register Map
422
DCMI Clocks
423
DCMI Introduction
423
DCMI Main Features
423
Digital Camera Interface (DCMI)
423
DCMI Block Diagram
424
DCMI Functional Overview
424
Figure 101. DCMI Block Diagram
424
DCMI Physical Interface
425
DMA Interface
425
Figure 102. Top-Level Block Diagram
425
Table 96. DCMI External Signals
425
Figure 103. DCMI Signal Waveforms
426
Table 97. Positioning of Captured Data Bytes in 32-Bit Words (8-Bit Width)
426
Table 98. Positioning of Captured Data Bytes in 32-Bit Words (10-Bit Width)
426
Synchronization
427
Table 100. Positioning of Captured Data Bytes in 32-Bit Words (14-Bit Width)
427
Table 99. Positioning of Captured Data Bytes in 32-Bit Words (12-Bit Width)
427
Figure 104. Timing Diagram
428
Capture Modes
430
Figure 105. Frame Capture Waveforms in Snapshot Mode
430
Crop Feature
431
Figure 106. Frame Capture Waveforms in Continuous Grab Mode
431
Figure 107. Coordinates and Size of the Window after Cropping
431
Fifo
432
Figure 108. Data Capture Waveforms
432
JPEG Format
432
Data Format Description
433
Data Formats
433
Figure 109. Pixel Raster Scan Order
433
Monochrome Format
433
Table 101. Data Storage in Monochrome Progressive Video Format
433
RGB Format
434
Table 102. Data Storage in RGB Progressive Video Format
434
Table 103. Data Storage in Ycbcr Progressive Video Format
434
Ycbcr Format
434
Ycbcr Format - y Only
434
DCMI Control Register (DCMI_CR)
435
DCMI Interrupts
435
DCMI Register Description
435
Half Resolution Image Extraction
435
Table 104. Data Storage in Ycbcr Progressive Video Format - y Extraction Mode
435
Table 105. DCMI Interrupts
435
DCMI Status Register (DCMI_SR)
439
DCMI Raw Interrupt Status Register (DCMI_RIS)
440
DCMI Interrupt Enable Register (DCMI_IER)
441
DCMI Masked Interrupt Status Register (DCMI_MIS)
442
DCMI Interrupt Clear Register (DCMI_ICR)
443
DCMI Embedded Synchronization Code Register (DCMI_ESCR)
444
DCMI Embedded Synchronization Unmask Register (DCMI_ESUR)
445
DCMI Crop Window Size (DCMI_CWSIZE)
446
DCMI Crop Window Start (DCMI_CWSTRT)
446
DCMI Data Register (DCMI_DR)
447
DCMI Register Map
448
Table 106. DCMI Register Map and Reset Values
448
Advanced-Control Timers (TIM1&TIM8)
449
TIM1&TIM8 Introduction
449
TIM1&TIM8 Main Features
449
Figure 110. Advanced-Control Timer Block Diagram
450
TIM1&TIM8 Functional Description
451
Time-Base Unit
451
Figure 111. Counter Timing Diagram with Prescaler Division Change from 1 to 2
452
Figure 112. Counter Timing Diagram with Prescaler Division Change from 1 to 4
452
Counter Modes
453
Figure 113. Counter Timing Diagram, Internal Clock Divided by 1
453
Figure 114. Counter Timing Diagram, Internal Clock Divided by 2
454
Figure 115. Counter Timing Diagram, Internal Clock Divided by 4
454
Figure 116. Counter Timing Diagram, Internal Clock Divided by N
454
Figure 117. Counter Timing Diagram, Update Event When ARPE=0
455
Figure 118. Counter Timing Diagram, Update Event When ARPE=1
455
Figure 119. Counter Timing Diagram, Internal Clock Divided by 1
457
Figure 120. Counter Timing Diagram, Internal Clock Divided by 2
457
Figure 121. Counter Timing Diagram, Internal Clock Divided by 4
458
Figure 122. Counter Timing Diagram, Internal Clock Divided by N
458
Figure 123. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
459
Figure 124. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
460
Figure 125. Counter Timing Diagram, Internal Clock Divided by 2
460
Figure 126. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
461
Figure 127. Counter Timing Diagram, Internal Clock Divided by N
461
Figure 128. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
462
Figure 129. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
462
Repetition Counter
462
Figure 130. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
464
Clock Selection
465
Figure 131. Control Circuit in Normal Mode, Internal Clock Divided by 1
465
Figure 132. TI2 External Clock Connection Example
466
Figure 133. Control Circuit in External Clock Mode 1
467
Figure 134. External Trigger Input Block
467
Capture/Compare Channels
468
Figure 135. Control Circuit in External Clock Mode 2
468
Figure 136. Capture/Compare Channel (Example: Channel 1 Input Stage)
469
Figure 137. Capture/Compare Channel 1 Main Circuit
469
Figure 138. Output Stage of Capture/Compare Channel (Channels 1 to 3)
470
Figure 139. Output Stage of Capture/Compare Channel (Channel 4)
470
Input Capture Mode
471
Figure 140. PWM Input Mode Timing
472
Forced Output Mode
472
PWM Input Mode
472
Output Compare Mode
473
Figure 141. Output Compare Mode, Toggle on OC1
474
PWM Mode
474
Figure 142. Edge-Aligned PWM Waveforms (ARR=8)
475
Figure 143. Center-Aligned PWM Waveforms (ARR=8)
476
Complementary Outputs and Dead-Time Insertion
477
Figure 144. Complementary Output with Dead-Time Insertion
478
Figure 145. Dead-Time Waveforms with Delay Greater than the Negative Pulse
478
Figure 146. Dead-Time Waveforms with Delay Greater than the Positive Pulse
478
Using the Break Function
479
Figure 147. Output Behavior in Response to a Break
481
Clearing the Ocxref Signal on an External Event
482
Figure 148. Clearing Timx Ocxref
482
6-Step PWM Generation
483
Figure 149. 6-Step Generation, COM Example (OSSR=1)
483
Figure 150. Example of One Pulse Mode
484
One-Pulse Mode
484
Encoder Interface Mode
485
Table 107. Counting Direction Versus Encoder Signals
486
Figure 151. Example of Counter Operation in Encoder Interface Mode
487
Figure 152. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
487
Interfacing with Hall Sensors
488
Timer Input XOR Function
488
Figure 153. Example of Hall Sensor Interface
489
Figure 154. Control Circuit in Reset Mode
490
Timx and External Trigger Synchronization
490
Figure 155. Control Circuit in Gated Mode
491
Figure 156. Control Circuit in Trigger Mode
492
Debug Mode
493
Figure 157. Control Circuit in External Clock Mode 2 + Trigger Mode
493
Timer Synchronization
493
TIM1&TIM8 Control Register 1 (Timx_Cr1)
494
TIM1&TIM8 Registers
494
TIM1&TIM8 Control Register 2 (Timx_Cr2)
495
TIM1&TIM8 Slave Mode Control Register (Timx_Smcr)
497
Table 108. Timx Internal Trigger Connection
499
TIM1&TIM8 Dma/Interrupt Enable Register (Timx_Dier)
499
TIM1&TIM8 Status Register (Timx_Sr)
501
TIM1&TIM8 Event Generation Register (Timx_Egr)
502
TIM1&TIM8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
504
TIM1&TIM8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
507
TIM1&TIM8 Capture/Compare Enable Register (Timx_Ccer)
508
Table 109. Output Control Bits for Complementary Ocx and Ocxn Channels
511
TIM1&TIM8 Auto-Reload Register (Timx_Arr)
512
TIM1&TIM8 Counter (Timx_Cnt)
512
TIM1&TIM8 Prescaler (Timx_Psc)
512
TIM1&TIM8 Capture/Compare Register 1 (Timx_Ccr1)
513
TIM1&TIM8 Repetition Counter Register (Timx_Rcr)
513
TIM1&TIM8 Capture/Compare Register 2 (Timx_Ccr2)
514
TIM1&TIM8 Capture/Compare Register 3 (Timx_Ccr3)
514
TIM1&TIM8 Break and Dead-Time Register (Timx_Bdtr)
515
TIM1&TIM8 Capture/Compare Register 4 (Timx_Ccr4)
515
TIM1&TIM8 DMA Control Register (Timx_Dcr)
517
TIM1&TIM8 DMA Address for Full Transfer (Timx_Dmar)
518
Table 110. TIM1&TIM8 Register Map and Reset Values
519
TIM1&TIM8 Register Map
519
General-Purpose Timers (TIM2 to TIM5)
521
TIM2 to TIM5 Introduction
521
TIM2 to TIM5 Main Features
521
Figure 158. General-Purpose Timer Block Diagram
522
TIM2 to TIM5 Functional Description
522
Time-Base Unit
522
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ST STM32F446 Series Application Note (50 pages)
Getting started with MCU hardware development
Brand:
ST
| Category:
Motherboard
| Size: 1 MB
Table of Contents
Table of Contents
2
1 Reference Documents
6
Table 2. Referenced Documents
6
2 Power Supplies
7
Digital Supply
7
Voltage Regulator
7
Regulator off Mode
7
Figure 1. BYPASS_REG Supervisor Reset Connection
8
Power Supply Schemes
9
Figure 2. Power Supply Scheme (Excluding Stm32F469Xx/F479Xx)
10
Figure 3. Power Supply Scheme for Stm32F469Xx/F479Xx
11
Analog Supply
12
3 Reset and Power Supply Supervisor
13
System Reset
13
NRST Circuitry Example
13
Figure 4. Reset Circuit
13
Figure 5. NRST Circuitry Example
14
Stm32F412Xx, Stm32F413Xx, Stm32F423Xx, Stm32F446Xx, Stm32F469Xx
14
And Stm32F479Xx)
14
Power Supply Supervisor
15
PDR_ON Circuitry Example
15
Figure 6. NRST Circuitry Timings Example
15
Stm32F411Xx, Stm32F412Xx, Stm32F413Xx, Stm32F423Xx, Stm32F446Xx
15
Stm32F469Xx and Stm32F479Xx)
15
Figure 7. PDR_ON Simple Circuitry Example
16
Stm32F411Xx, Stm32F413Xx, Stm32F423Xx, Stm32F412Xx, Stm32F446Xx
16
Power on Reset (POR) / Power down Reset (PDR)
17
Figure 8. PDR_ON Timings Example
17
Programmable Voltage Detector (PVD)
18
Figure 9. Power-On Reset/Power-Down Reset Waveform
18
Figure 10. PVD Thresholds
19
4 Package
20
Package Selection
20
Table 3. Package Summary
20
Pinout Compatibility
22
I/O Speed
22
Table 4. I/O AC Characteristics
22
Alternate Function
24
Table 5. Alternate Function
24
Handling Unused Pins
25
Boot Mode Selection
25
Figure 11. Stm32Cubemx Example Screen-Shot
25
Table 6. Boot Modes
26
Boot Pin Connection
27
Embedded Boot Loader Mode
27
Table 7. Stm32F4Xxxx Bootloader Communication Peripherals
27
Figure 12. Boot Mode Selection Implementation Example
27
5 Debug Management
29
SWJ Debug Port (Serial Wire and JTAG)
29
Pinout and Debug Port Pins
29
SWJ Debug Port Pins
29
Figure 13. Host-To-Board Connection
29
Internal Pull-Up and Pull-Down Resistors on JTAG Pins
30
SWJ Debug Port Connection with Standard JTAG Connector
30
Table 8. Debug Port Pin Assignment
30
Figure 14. JTAG Connector Implementation
31
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