Power Status Register 1 (Pwr_Sr1) - ST STM32L4x6 Reference Manual

RM0351
Bits 31:10 Reserved, must be kept at reset value.
Bit 9 VBRS: V
Bit 8 VBE: V
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 WP5: Wakeup pin WKUP5 polarity
Bit 3 WP4: Wakeup pin WKUP4 polarity
Bit 2 WP3: Wakeup pin WKUP3 polarity
Bit 1 WP2: Wakeup pin WKUP2 polarity
Bit 0 WP1: Wakeup pin WKUP1 polarity
Power status register 1 ( PWR_SR1 )
5.4.5
Address offset: 0x10
Reset value: 0x0000 0000. This register is not reset when exiting Standby modes and with
the PWRRST bit in the RCC_APB1RSTR1 register.
Access: 2 additional APB cycles are needed to read this register vs. a standard APB read.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
WUFI Res. Res. Res.
r
battery charging resistor selection
BAT
0: Charge V through a 5 kOhms resistor
BAT
1: Charge V through a 1.5 kOhms resistor
BAT
battery charging enable
BAT
0: V battery charging disable
BAT
1: V battery charging enable
BAT
This bit defines the polarity used for an event detection on external wake-up pin, WKUP5
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
This bit defines the polarity used for an event detection on external wake-up pin, WKUP4
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
This bit defines the polarity used for an event detection on external wake-up pin, WKUP3
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
This bit defines the polarity used for an event detection on external wake-up pin, WKUP2
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
This bit defines the polarity used for an event detection on external wake-up pin, WKUP1
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res.
8 7 6
SBF Res. Res.
r
DocID024597 Rev 3
Power control (PWR)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
Res. WUF5 WUF4 WUF3
r r r
17 16
Res. Res.
1 0
WUF2 WUF1
r r
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