Timx Capture/Compare Register 2 (Timx_Ccr2) - ST STM32L4x6 Reference Manual

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
15 14 13
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Bits 31:16 CCR1[31:16]: High Capture/Compare 1 value (on TIM2 and TIM5)
Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value
If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit
OC1PE). Else the preload value is copied in the active capture/compare 1 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1).
27.4.14

TIMx capture/compare register 2 (TIMx_CCR2)

Address offset: 0x38
Reset value: 0x00000000
31 30 29
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15 14 13
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Bits 31:16 CCR2[31:16]: High Capture/Compare 2 value (on TIM2 and TIM5)
Bits 15:0 CCR2[15:0]: Low Capture/Compare 2 value
If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit
OC2PE). Else the preload value is copied in the active capture/compare 2 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2).
27.4.15 TIMx capture/compare register 3 (TIMx_CCR3)
Address offset: 0x3C
Reset value: 0x0000
31 30 29
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922/1693
12 11 10 9
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28 27 26 25
CCR2[31:16] (depending on timers)
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12 11 10 9
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28 27 26 25
CCR3[31:16] (depending on timers)
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DocID024597 Rev 3
8 7 6 5
CCR1[15:0]
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24 23 22 21
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8 7 6 5
CCR2[15:0]
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24 23 22 21
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4 3 2 1
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20 19 18 17
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4 3 2 1
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20 19 18 17
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RM0351
0
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16
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0
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16
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