Common Registers) Offset =0X300) - ST STM32L4x6 Reference Manual

Analog-to-digital converters (ADC)
Table 100. ADC register map and reset values for each ADC (offset=0x000
Offset Register
ADCx_CALFACT
0xB4
Reset value
Table 101. ADC register map and reset values (master and slave ADC
Offset Register
ADCx_CSR
0x00
Reset value
0x04 Reserved
ADCx_CCR
0x08
Reset value
ADCx_CDR
0x0C
Reset value 0
Refer to
boundary addresses.
540/1693
for master ADC, 0x100 for slave ADC) (continued)

common registers) offset =0x300)

0 0 0 0
0 0
RDATA_SLV[15:0]
0 0 0 0 0 0 0 0
Section 2.2.2: Memory map and register boundary addresses
CALFACT_D[6:0]
0 0 0 0 0 0 0
slave ADC2
0 0 0 0 0 0 0
Res.
PRESC[3:0]
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
DocID024597 Rev 3
0
master ADC1
0 0 0 0 0
DELAY[3:0]
0 0 0 0 0 0
RDATA_MST[15:0]
0 0 0 0 0 0 0 0 0
for the register
RM0351
CALFACT_S[6:0]
0 0 0 0 0 0
0 0 0 0 0 0
DUAL[4:0]
0 0 0 0 0
0 0 0 0 0 0