Table 48. Nand Memory Mapping And Timing Registers; Table 49. Nand Bank Selection; Nand Flash Memory Address Mapping - ST STM32L4x6 Reference Manual

Flexible static memory controller (FSMC)
1. In case of a 16-bit external memory width, the FMC will internally use HADDR[25:1] to generate the
address for external memory FMC_A[24:0].
Whatever the external memory width, FMC_A[0] should be connected to external memory address A[0].
14.4.2

NAND Flash memory address mapping

The NAND bank is divided into memory areas as indicated in
Start address
0x8800 0000
0x8000 0000
For NAND Flash memory, the common and attribute memory spaces are subdivided into
three sections (see in
•
Data section (first 64 Kbytes in the common/attribute memory space)
•
Command section (second 64 Kbytes in the common / attribute memory space)
•
Address section (next 128 Kbytes in the common / attribute memory space)
Section name
Address section
Command section
Data section
The application software uses the 3 sections to access the NAND Flash memory:
•
To sending a command to NAND Flash memory, the software must write the
command value to any memory location in the command section.
•
To specify the NAND Flash address that must be read or written, the software
must write the address value to any memory location in the address section. Since an
address can be 4 or 5 bytes long (depending on the actual memory size), several
consecutive write operations to the address section are required to specify the full
address.
•
To read or write data, the software reads or writes the data from/to any memory
location in the data section.
Since the NAND Flash memory automatically increments addresses, there is no need to
increment the address of the data section to access consecutive memory locations.
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Table 48. NAND memory mapping and timing registers

End address FMC bank
0x8BFF FFFF
Bank 3 - NAND Flash
0x83FF FFFF
Table 49 below) located in the lower 256 Kbytes:

Table 49. NAND bank selection

HADDR[17:16]
DocID024597 Rev 3
Memory space
Attribute
Common
1X
01
00
RM0351
Table 48.
Timing register
FMC_PATT (0x8C)
FMC_PMEM (0x88)
Address range
0x020000-0x03FFFF
0x010000-0x01FFFF
0x000000-0x0FFFF