Ahb2 Peripheral Reset Register (Rcc_Ahb2Rstr) - ST STM32L4x6 Reference Manual

RM0351
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 DMA2RST: DMA2 reset
Bit 0 DMA1RST: DMA1 reset
6.4.11

AHB2 peripheral reset register (RCC_AHB2RSTR)

Address offset: 0x2C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res.
15 14 13
ADC
OTGFS
Res. Res.
RST
rw
Bits 31:19 Reserved, must be kept at reset value.
Bit 18 RNGRST: Random number generator reset
Bit 17 Reserved, must be kept at reset value.
Bit 16 AESRST: AES hardware accelerator reset
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 ADCRST: ADC reset
Bit 12 OTGFSRST: USB OTG FS reset
Bits 11:8 Reserved, must be kept at reset value.
Set and cleared by software.
0: No effect
1: Reset DMA2
Set and cleared by software.
0: No effect
1: Reset DMA1
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
Res. Res. Res.
RST
Set and cleared by software.
0: No effect
1: Reset RNG
Set and cleared by software.
0: No effect
1: Reset AES
Set and cleared by software.
0: No effect
1: Reset ADC interface
Set and cleared by software.
0: No effect
1: Reset USB OTG FS
24 23 22
Res. Res. Res.
8 7 6
GPIOH GPIOG
Res.
RST RST
rw rw
DocID024597 Rev 3
Reset and clock control (RCC)
21 20 19 18
RNG
Res. Res. Res.
RST
rw
5 4 3
GPIOF GPIOE GPIOD GPIOC
RST RST RST RST
rw rw rw rw
17 16
AES
Res.
RST
rw
2 1 0
GPIOB GPIOA
RST RST
rw rw
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