ST STM32L4x6 Reference Manual page 152

Power control (PWR)
HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx (x=1,2,3),
U(S)ARTx(x=1,2...5) and LPUART) can switch on the HSI16 to receive a frame, and switch
off the HSI16 after receiving the frame if it is not a wakeup frame. In this case, the HSI16
clock is propagated only to the peripheral requesting it.
SRAM1, SRAM2 and register contents are preserved.
The BOR is always available in Stop 0 mode. The consumption is increased when
thresholds higher than V
I/O states in Stop 0 mode
In the Stop 0 mode, all I/O pins keep the same state as in the Run mode.
Entering the Stop 0 mode
The Stop 0 mode is entered according
SLEEPDEEP bit in the Cortex
Refer to
If Flash memory programming is ongoing, the Stop 0 mode entry is delayed until the
memory access is finished.
If an access to the APB domain is ongoing, The Stop 0 mode entry is delayed until the APB
access is finished.
In Stop 0 mode, the following features can be selected by programming individual control
bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started, it cannot be stopped except by a Reset. See
Section 32.3: IWDG functional
• real-time clock (RTC): this is configured by the RTCEN bit in the
control register (RCC_BDCR)
•
Internal RC oscillator (LSI): this is configured by the LSION bit in the
register
•
External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the
domain control register
Several peripherals can be used in Stop 0 mode and can add consumption if they are
enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LCD, LPTIM1,
LPTIM2, I2Cx (x=1,2,3) U(S)ARTx(x=1,2...5), LPUART.
The DACx (x=1,2), the OPAMPs and the comparators can be used in Stop 0 mode, the
PVMx (x=1,2,3,4) and the PVD as well. If they are not needed, they must be disabled by
software to save their power consumptions.
The ADCx (x=1,2,3), temperature sensor and VREFBUF buffer can consume power during
the Stop 0 mode, unless they are disabled before entering this mode.
Exiting the Stop 0 mode
The Stop 0 mode is exit according
Refer to
When exiting Stop 0 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is
selected as system clock if the bit STOPWUCK is set in
152/1693
BOR0
®
Table 24: Stop 0 mode
(RCC_CSR).
(RCC_BDCR).
Table 24: Stop 0 mode
are used.
Section : Entering low power
-M4 System Control register is set.
for details on how to enter the Stop 0 mode.
description.
Section : Entering low power
for details on how to exit Stop 0 mode.
DocID024597 Rev 3
mode, when the
Backup domain
Control/status
mode.
Clock configuration register
RM0351
Backup