ST STM32L4x6 Reference Manual page 852

Advanced-control timers (TIM1/TIM8)
Table 150. TIM1 register map and reset values (continued)
Offset Register
TIM1_CCMR1
Output
Compare mode
Reset value
0x18
TIM1_CCMR1
Input Capture
mode
Reset value
TIM1_CCMR2
Output
Compare mode
Reset value
0x1C
TIM1_CCMR2
Input Capture
mode
Reset value
TIM1_CCER
0x20
Reset value
TIM1_CNT
0x24
Reset value 0
TIM1_PSC
0x28
Reset value
TIM1_ARR
0x2C
Reset value
TIM1_RCR
0x30
Reset value
TIM1_CCR1
0x34
Reset value
TIM1_CCR2
0x38
Reset value
TIM1_CCR3
0x3C
Reset value
TIM1_CCR4
0x40
Reset value
852/1693
0 0
0 0
0 0 0 0
DocID024597 Rev 3
CC2
OC2M
S
[2:0]
[1:0]
0 0 0 0 0 0 0 0 0
IC2 CC2
IC2F[3:0] PSC S
[1:0] [1:0]
0 0 0 0 0 0 0 0 0
CC4
OC4M
S
[2:0]
[1:0]
0 0 0 0 0 0 0 0 0
IC4 CC4
IC4F[3:0] PSC S
[1:0] [1:0]
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
CNT[15:0]
0 0 0 0 0 0 0 0 0
PSC[15:0]
0 0 0 0 0 0 0 0 0
ARR[15:0]
1 1 1 1 1 1 1 1 1
REP[15:0]
0 0 0 0 0 0 0 0 0
CCR1[15:0]
0 0 0 0 0 0 0 0 0
CCR2[15:0]
0 0 0 0 0 0 0 0 0
CCR3[15:0]
0 0 0 0 0 0 0 0 0
CCR4[15:0]
0 0 0 0 0 0 0 0 0
RM0351
CC1
OC1M
S
[2:0]
[1:0]
0 0 0 0 0 0 0
IC1 CC1
IC1F[3:0] PSC S
[1:0] [1:0]
0 0 0 0 0 0 0
CC3
OC3M
S
[2:0]
[1:0]
0 0 0 0 0 0 0
IC3 CC3
IC3F[3:0] PSC S
[1:0] [1:0]
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
1 1 1 1 1 1 1
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0