Aes Initialization Vector Register 2 (Aes_Ivr2) (Ivr[95:64]) - ST STM32L4x6 Reference Manual

Advanced encryption standard hardware accelerator (AES)

25.14.11 AES initialization vector register 2 (AES_IVR2) (IVR[95:64])

Address offset: 0x28
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
Bits 31:0 IVR2[31:0]: Initialization vector register (IVR[95:64])
This register must be written before the EN bit in the AES_CR register is set:
The register value has no meaning if:
– The ECB mode (electronic codebook) is selected.
– The CTR or CBC mode is selected in addition with the key derivation or key derivation + decryption
mode.
In CTR mode (counter mode), this register contains the nonce value.
Reading this register while AES is enabled will return the value 0x00000000.
25.14.12 AES initialization vector register 3 (AES_IVR3) (MSB: IVR[127:96])
Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
Bits 31:0 IVR3[31:0]: Initialization vector register (MSB IVR[127:96])
This register must be written before the EN bit in the AES_CR register is set:
The register value has no meaning if:
– The ECB mode (electronic codebook) is selected.
– The CTR or CBC mode is selected in addition with the key derivation or key derivation + decryption
mode.
In CTR mode (counter mode), this register contains the nonce value.
Reading this register while AES is enabled will return the value 0x00000000.
25.14.13 AES key register 4 (AES_KEYR4) (key[159:128])
Address offset: 0x30
Reset value: 0x0000 0000
746/1693
27 26 25 24
rw rw rw rw
11 10 9 8
rw rw rw rw
27 26 25 24
rw rw rw rw
11 10 9 8
rw rw rw rw
DocID024597 Rev 3
23 22 21
IVR2[31:16]
rw rw rw
7 6 5
IVR2[15:0]
rw rw rw
23 22 21
IVR3[31:16]
rw rw rw
7 6 5
IVR3[15:0]
rw rw rw
20 19 18 17
rw rw rw rw
4 3 2 1
rw rw rw rw
20 19 18 17
rw rw rw rw
4 3 2 1
rw rw rw rw
RM0351
16
rw
0
rw
16
rw
0
rw