Figure 132. Timing Diagram For Conversion With Trigger Disabled Ten = 0; Dac Output Voltage - ST STM32L4x6 Reference Manual

RM0351

Figure 132. Timing diagram for conversion with trigger disabled TEN = 0

APB1_CLK
17.3.5

DAC output voltage

Digital inputs are converted to output voltages on a linear conversion between 0 and V
The analog output voltages on each DAC channel pin are determined by the following
equation:
DACoutput
17.3.6 DAC trigger selection
If the TENx control bit is set, conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8 possi-
ble events will trigger conversion as shown in bits TSEL1[2:0] and TSEL2[2:0] in
Section 17.5.1: DAC control register
Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on
the selected external interrupt line 9, the last data stored into the DAC_DHRx register are
transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1
cycles after the trigger occurs.
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the
DAC_DHRx register contents.
Note: 1 TSELx[2:0] bit cannot be changed when the ENx bit is set.
2 When software trigger is selected, the transfer from the DAC_DHRx register to the
DAC_DORx register takes only one APB clock cycle.
17.3.7 DMA request
Each DAC channel has a DMA capability. Two DMA channels are used to service DAC
channel DMA requests.
A DAC DMA request is generated when an external trigger (but not a software trigger)
occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred
into the DAC_DORx register.
In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one
DMA request is needed, you should set only the corresponding DMAENx bit. In this way, the
application can manage both DAC channels in dual mode by using one DMA request and a
unique DMA channel.
DHR 0x1AC
DOR
DOR
×
V
= ------------- -
REF
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DocID024597 Rev 3
Digital-to-analog converter (DAC)
0x1AC
t
SETTLING
(DAC_CR).
Output voltage
available on DAC_OUT pin
ai14711b
545/1693
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REF+
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