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Reset and clock control (RCC)
Bit 2 MSIRDYC: MSI ready interrupt clear
Bit 1 LSERDYC: LSE ready interrupt clear
Bit 0 LSIRDYC: LSI ready interrupt clear
6.4.10
AHB1 peripheral reset register (RCC_AHB1RSTR)
Address offset: 0x28
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 TSCRST: Touch Sensing Controller reset
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCRST: CRC reset
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 FLASHRST: Flash memory interface reset
216/1693
This bit is set by software to clear the MSIRDYF flag.
0: No effect
1: MSIRDYF cleared
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
CRC
Res.
Res.
Res.
RST
rw
Set and cleared by software.
0: No effect
1: Reset TSC
Set and cleared by software.
0: No effect
1: Reset CRC
Set and cleared by software. This bit can be activated only when the Flash memory is in
power down mode.
0: No effect
1: Reset Flash memory interface
24
23
22
Res.
Res.
Res.
8
7
6
FLASH
Res.
Res.
RST
rw
DocID024597 Rev 3
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
RM0351
17
16
TSC
Res.
RST
rw
1
0
DMA2
DMA1
RST
RST
rw
rw
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