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Reset and clock control (RCC)
Bit 4 GPIOESMEN: IO port E clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port E clocks disabled by the clock gating
1: IO port E clocks enabled by the clock gating
Bit 3 GPIODSMEN: IO port D clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port D clocks disabled by the clock gating
1: IO port D clocks enabled by the clock gating
Bit 2 GPIOCSMEN: IO port C clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port C clocks disabled by the clock gating
1: IO port C clocks enabled by the clock gating
Bit 1 GPIOBSMEN: IO port B clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port B clocks disabled by the clock gating
1: IO port B clocks enabled by the clock gating
Bit 0 GPIOASMEN: IO port A clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port A clocks disabled by the clock gating
1: IO port A clocks enabled by the clock gating
1. This register only configures the clock gating, not the clock source itself. Most of the peripherals are clocked by a single
clock (AHB or APB clock), which is always disabled in Stop mode. In this case setting the bit has no effect in Stop mode.
6.4.24
AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR)
Address offset: 0x70
Reset value: 0x00000 0101
Access: no wait state, word, half-word and byte access
31
30
29
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Bits 31:9 Reserved, must be kept at reset value.
236/1693
28
27
26
25
Res.
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Res.
DocID024597 Rev 3
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
(1)
during Sleep and Stop modes
24
23
22
21
Res.
Res.
Res.
Res.
8
7
6
5
QSPI
Res.
Res.
Res.
SMEN
rw
20
19
18
17
Res.
Res.
Res.
Res.
4
3
2
1
Res.
Res.
Res.
Res.
RM0351
16
Res.
0
FMC
SMEN
rw
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