Figure 168. Charge Transfer Acquisition Sequence - ST STM32L4x6 Reference Manual

RM0351
23.3.4 Charge transfer acquisition sequence
An example of a charge transfer acquisition sequence is detailed in
For higher flexibility, the charge transfer frequency is fully configurable. Both the pulse high
state (charge of C
be defined using the CTPH[3:0] and CTPL[3:0] bits in the TSC_CR register. The standard
range for the pulse high and low states duration is 500 ns to 2 µs. To ensure a correct
measurement of the electrode capacitance, the pulse high state duration must be set to
ensure that C
A dead time where both the sampling capacitor I/O and the channel I/O are in input floating
state is inserted between the pulse high and low states to ensure an optimum charge
transfer acquisition sequence. This state duration is 1 periods of HCLK.
At the end of the pulse high state and if the spread spectrum feature is enabled, a variable
number of periods of the SSCLK clock are added.
The reading of the sampling capacitor I/O, to determine if the voltage across C
reached the given threshold, is performed at the end of the pulse low state and its duration
is one period of HCLK.
Note: The following TSC control register configurations are forbidden:
•
bits PGPSC are set to "0" and bits CTPL are set to "0"
•
bits PGPSC are set to "0" and bits CTPL are set to "1"
•
bits PGPSC are set to "1" and bits CTPL are set to "0"

Figure 168. Charge transfer acquisition sequence

) and the pulse low state (transfer of charge from C
X
is always fully charged.
X
DocID024597 Rev 3
Touch sensing controller (TSC)
Figure 168.
to C ) duration can
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