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STM32F40 Series
ST STM32F40 Series Manuals
Manuals and User Guides for ST STM32F40 Series. We have
2
ST STM32F40 Series manuals available for free PDF download: Reference Manual, Programming Manual
ST STM32F40 Series Reference Manual (1422 pages)
Brand:
ST
| Category:
Microcontrollers
| Size: 15.05 MB
Table of Contents
Table 1. Applicable Products
1
Table of Contents
2
Documentation Conventions
47
List of Abbreviations for Registers
47
Glossary
48
Peripheral Availability
48
Memory and Bus Architecture
49
System Architecture
49
Figure 1. System Architecture for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx Devices
50
Figure 2. System Architecture for Stm32F42Xxx and Stm32F43Xxx Devices
50
S0: I-Bus
51
S1: D-Bus
51
S2: S-Bus
51
S3, S4: DMA Memory Bus
51
S5: DMA Peripheral Bus
51
S6: Ethernet DMA Bus
51
S7: USB OTG HS DMA Bus
51
Busmatrix
51
AHB/APB Bridges (APB)
52
Memory Organization
52
Memory Map
52
Table 2. Stm32F4Xx Register Boundary Addresses
52
Embedded SRAM
55
Flash Memory Overview
55
Bit Banding
55
Boot Configuration
56
Table 3. Boot Modes
56
Table 4. Memory Mapping Vs. Boot Mode/Physical Remap
57
Embedded Flash Memory Interface
59
Introduction
59
Main Features
59
Figure 3. Flash Memory Interface Connection Inside System Architecture
59
Embedded Flash Memory
60
Table 5. Flash Module Organization (Stm32F40X and Stm32F41X)
60
Read Interface
61
Relation between CPU Clock Frequency and Flash Memory Read Time
61
Table 6. Flash Memory Organization (Stm32F42X and Stm32F43X)
61
Number of Wait States According to CPU Clock (HCLK) Frequency
62
Adaptive Real-Time Memory Accelerator (ART Accelerator™)
63
Figure 4. Sequential 32-Bit Instruction Execution
64
Erase and Program Operations
65
Unlocking the Flash Control Register
65
Program/Erase Parallelism
66
Erase
66
Table 8. Program/Erase Parallelism
66
Programming
67
Interrupts
68
Option Bytes
68
Description of User Option Bytes
68
Table 9. Flash Interrupt Request
68
Table 10. Option Byte Organization
68
Table 11. Description of the Option Bytes (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
69
Table 12. Description of the Option Bytes (Stm32F42Xxx and Stm32F43Xxx)
70
Programming User Option Bytes
71
Read Protection (RDP)
72
Write Protections
73
Table 13. Access Versus Read Protection Level
73
Figure 5. RDP Levels
73
One-Time Programmable Bytes
74
Table 14. OTP Area Organization
74
Flash Interface Registers
75
Flash Access Control Register (FLASH_ACR)
75
Flash Key Register (FLASH_KEYR)
77
Flash Option Key Register (FLASH_OPTKEYR)
77
Flash Status Register (FLASH_SR)
78
Flash Control Register (FLASH_CR) for
79
Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
79
Stm32F42Xxx and Stm32F43Xxx
80
Flash Option Control Register (FLASH_OPTCR)
82
Flash Option Control Register (FLASH_OPTCR1)
83
For Stm32F42Xxx and Stm32F43Xxx
83
Flash Interface Register Map
84
Table 15. Flash Register Map and Reset Values (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
84
Table 16. Flash Register Map and Reset Values (Stm32F42Xxx and Stm32F43Xxx)
84
CRC Calculation Unit
86
CRC Introduction
86
CRC Main Features
86
CRC Functional Description
86
Figure 6. CRC Calculation Unit Block Diagram
86
CRC Registers
87
Data Register (CRC_DR)
87
Independent Data Register (CRC_IDR)
87
Control Register (CRC_CR)
88
CRC Register Map
88
Table 17. CRC Calculation Unit Register Map and Reset Values
88
Power Controller (PWR)
89
Power Supplies
89
Figure 7. Power Supply Overview
89
Independent A/D Converter Supply and Reference Voltage
90
Battery Backup Domain
90
Voltage Regulator
92
Figure 8. Backup Domain
92
Power Supply Supervisor
94
Power-On Reset (Por)/Power-Down Reset (PDR)
94
Brownout Reset (BOR)
94
Figure 9. Power-On Reset/Power-Down Reset Waveform
94
Programmable Voltage Detector (PVD)
95
Figure 10. BOR Thresholds
95
Low-Power Modes
96
Figure 11. PVD Thresholds
96
Slowing down System Clocks
97
Peripheral Clock Gating
97
Table 18. Low-Power Mode Summary
97
Sleep Mode
98
Table 19. Sleep-Now Entry and Exit
98
Stop Mode
99
Table 20. Sleep-On-Exit Entry and Exit
99
Table 21. Stop Operating Modes
100
Table 22. Stop Mode Entry and Exit
100
Standby Mode
101
Table 23. Standby Mode Entry and Exit
101
Programming the RTC Alternate Functions to Wake up the Device from the Stop and Standby Modes
102
Power Control Registers
105
PWR Power Control Register (PWR_CR)
105
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
105
PWR Power Control Register (PWR_CR)
106
For Stm32F42Xxx and Stm32F43Xxx
106
PWR Power Control/Status Register (PWR_CSR)
108
PWR Register Map
109
Table 24. PWR - Register Map and Reset Values for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
109
Table 25. PWR - Register Map and Reset Values for Stm32F42Xxx and Stm32F43Xxx
110
Reset and Clock Control for (RCC)
111
Reset
111
System Reset
111
Power Reset
112
Figure 12. Simplified Diagram of the Reset Circuit
112
Backup Domain Reset
113
Clocks
113
Figure 13. Clock Tree
114
HSE Clock
116
Figure 14. HSE/ LSE Clock Sources
116
HSI Clock
117
PLL Configuration
117
LSE Clock
118
LSI Clock
118
System Clock (SYSCLK) Selection
118
Clock Security System (CSS)
118
RTC/AWU Clock
119
Watchdog Clock
120
Clock-Out Capability
120
Internal/External Clock Measurement Using TIM5/TIM11
120
Figure 15. Frequency Measurement with TIM5 in Input Capture Mode
121
Figure 16. Frequency Measurement with TIM11 in Input Capture Mode
122
RCC Registers
123
RCC Clock Control Register (RCC_CR)
123
RCC PLL Configuration Register (RCC_PLLCFGR)
125
RCC Clock Configuration Register (RCC_CFGR)
127
RCC Clock Interrupt Register (RCC_CIR)
129
RCC AHB1 Peripheral Reset Register (RCC_AHB1RSTR)
132
RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR)
134
RCC AHB3 Peripheral Reset Register (RCC_AHB3RSTR)
135
RCC APB1 Peripheral Reset Register for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx(RCC_APB1RSTR)
135
RCC APB1 Peripheral Reset Register for
138
Stm32F42Xxx and Stm32F43Xxx (RCC_APB1RSTR)
138
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
141
RCC APB2 Peripheral Reset Register for Stm32F42Xxx and Stm32F43Xxx (RCC_APB2RSTR)
143
RCC AHB1 Peripheral Clock Enable Register (RCC_AHB1ENR)
145
RCC AHB2 Peripheral Clock Enable Register (RCC_AHB2ENR)
147
RCC AHB3 Peripheral Clock Enable Register (RCC_AHB3ENR)
148
RCC APB1 Peripheral Clock Enable Register for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx(RCC_APB1ENR)
148
RCC APB1 Peripheral Clock Enable Register for Stm32F42Xxx and Stm32F43Xxx(RCC_APB1ENR)
151
RCC APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
154
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
154
RCC APB2 Peripheral Clock Enable Register for Stm32F42Xxx and Stm32F43Xxx(RCC_APB2ENR)
156
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx (RCC_AHB1LPENR)
158
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register for Stm32F42Xxx and Stm32F43Xxx (RCC_AHB1LPENR)
161
RCC AHB2 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB2LPENR)
163
RCC AHB3 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB3LPENR)
164
RCC APB1 Peripheral Clock Enable in Low Power Mode Register for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx (RCC_APB1LPENR)
165
RCC APB1 Peripheral Clock Enable in Low Power Mode Register for Stm32F42Xxx and Stm32F43Xxx (RCC_APB1LPENR)
168
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx(RCC_APB2LPENR)
171
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register for Stm32F42Xxx and Stm32F43Xxx (RCC_APB2LPENR)
173
RCC Backup Domain Control Register (RCC_BDCR)
175
RCC Clock Control & Status Register (RCC_CSR)
176
RCC Spread Spectrum Clock Generation Register (RCC_SSCGR)
178
RCC PLLI2S Configuration Register (RCC_PLLI2SCFGR)
179
RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR)
180
RCC Register Map
181
Table 26. RCC Register Map and Reset Values for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
181
Table 27. RCC Register Map and Reset Values for Stm32F42Xxx and Stm32F43Xxx
183
General-Purpose I/Os (GPIO)
185
GPIO Introduction
185
GPIO Main Features
185
GPIO Functional Description
185
Figure 17. Basic Structure of a Five-Volt Tolerant I/O Port Bit
186
General-Purpose I/O (GPIO)
187
Table 28. Port Bit Configuration Table
187
I/O Pin Multiplexer and Mapping
188
Table 29. Flexible SWJ-DP Pin Assignment
189
Figure 18. Selecting an Alternate Function on Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
190
I/O Port Control Registers
191
Figure 19. Selecting an Alternate Function on Stm32F42Xxx and Stm32F43Xxx
191
I/O Port Data Registers
192
I/O Data Bitwise Handling
192
GPIO Locking Mechanism
192
I/O Alternate Function Input/Output
193
External Interrupt/Wakeup Lines
193
Input Configuration
193
Output Configuration
194
Figure 20. Input Floating/Pull Up/Pull down Configurations
194
Alternate Function Configuration
195
Figure 21. Output Configuration
195
Figure 22. Alternate Function Configuration
195
Analog Configuration
196
Using the OSC32_IN/OSC32_OUT Pins as GPIO PC14/PC15
196
Port Pins
196
Using the OSC_IN/OSC_OUT Pins as GPIO PH0/PH1 Port Pins
196
Figure 23. High Impedance-Analog Configuration
196
Selection of RTC_AF1 and RTC_AF2 Alternate Functions
197
Table 30. RTC_AF1 Pin
197
GPIO Registers
198
GPIO Port Mode Register (Gpiox_Moder) (X = A..I
198
Table 31. RTC_AF2 Pin
198
GPIO Port Output Type Register (Gpiox_Otyper)
199
(X = a
199
GPIO Port Output Speed Register (Gpiox_Ospeedr)
199
GPIO Port Pull-Up/Pull-Down Register (Gpiox_Pupdr)
199
GPIO Port Input Data Register (Gpiox_Idr) (X = A..I
200
GPIO Port Output Data Register (Gpiox_Odr) (X = A..I
200
GPIO Port Bit Set/Reset Register (Gpiox_Bsrr) (X = A..I
201
GPIO Port Configuration Lock Register (Gpiox_Lckr)
201
(X = a
201
GPIO Alternate Function Low Register (Gpiox_Afrl) (X = A..I
202
(X = a
203
GPIO Register Map
203
Table 32. GPIO Register Map and Reset Values
203
System Configuration Controller (SYSCFG)
206
I/O Compensation Cell
206
SYSCFG Registers
206
SYSCFG Memory Remap Register (SYSCFG_MEMRMP)
206
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
207
For Stm32F42Xxx and Stm32F43Xxx
207
SYSCFG External Interrupt Configuration Register 1
208
(Syscfg_Exticr1)
208
SYSCFG External Interrupt Configuration Register 2
209
(Syscfg_Exticr2)
209
(Syscfg_Exticr3)
209
SYSCFG External Interrupt Configuration Register 4
210
(Syscfg_Exticr4)
210
Compensation Cell Control Register (SYSCFG_CMPCR)
210
SYSCFG Register Maps
211
Table 33. SYSCFG Register Map and Reset Values Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
211
Table 34. SYSCFG Register Map and Reset Values (Stm32F42Xxx and Stm32F43Xxx)
212
DMA Controller (DMA)
213
DMA Introduction
213
DMA Main Features
213
DMA Functional Description
215
General Description
215
Figure 24. DMA Block Diagram
215
Figure 25. System Implementation of the Two DMA Controllers (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
216
DMA Transactions
217
Figure 26. System Implementation of the Two DMA Controllers (Stm32F42Xxx and Stm32F43Xxx)
217
Channel Selection
218
Table 35. DMA1 Request Mapping
218
Figure 27. Channel Selection
218
Arbiter
219
Table 36. DMA2 Request Mapping
219
DMA Streams
220
Source, Destination and Transfer Modes
220
Table 37. Source and Destination Address
220
Figure 28. Peripheral-To-Memory Mode
221
Figure 29. Memory-To-Peripheral Mode
222
Pointer Incrementation
223
Figure 30. Memory-To-Memory Mode
223
Circular Mode
224
Double Buffer Mode
224
Programmable Data Width, Packing/Unpacking, Endianess
225
Table 38. Source and Destination Address Registers in Double Buffer Mode (DBM=1)
225
Table 39. Packing/Unpacking & Endian Behavior (Bit PINC = MINC = 1)
226
Table 40. Restriction on NDT Versus PSIZE and MSIZE
226
Single and Burst Transfers
227
Fifo
227
Figure 31. FIFO Structure
228
Table 41. FIFO Threshold Configurations
229
DMA Transfer Completion
230
DMA Transfer Suspension
231
Flow Controller
231
Summary of the Possible DMA Configurations
232
Table 42. Possible DMA Configurations
232
Stream Configuration Procedure
233
Error Management
234
DMA Interrupts
235
DMA Registers
235
DMA Low Interrupt Status Register (DMA_LISR)
235
Table 43. DMA Interrupt Requests
235
DMA High Interrupt Status Register (DMA_HISR)
236
DMA Low Interrupt Flag Clear Register (DMA_LIFCR)
237
DMA High Interrupt Flag Clear Register (DMA_HIFCR)
237
DMA Stream X Configuration Register (Dma_Sxcr) (X = 0
239
DMA Stream X Number of Data Register (Dma_Sxndtr) (X = 0
242
DMA Stream X Peripheral Address Register (Dma_Sxpar) (X = 0
242
DMA Stream X Memory 0 Address Register (Dma_Sxm0Ar) (X = 0
243
DMA Stream X Memory 1 Address Register (Dma_Sxm1Ar) (X = 0
243
DMA Stream X FIFO Control Register (Dma_Sxfcr) (X = 0
244
DMA Register Map
245
Table 44. DMA Register Map and Reset Values
245
Interrupts and Events
249
Nested Vectored Interrupt Controller (NVIC)
249
NVIC Features
249
Systick Calibration Value Register
249
Interrupt and Exception Vectors
249
External Interrupt/Event Controller (EXTI)
249
Table 45. Vector Table for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
250
Table 46. Vector Table for Stm32F42Xxx and Stm32F43Xxx
253
EXTI Main Features
257
EXTI Block Diagram
257
Wakeup Event Management
257
Figure 32. External Interrupt/Event Controller Block Diagram
257
Functional Description
258
External Interrupt/Event Line Mapping
259
Figure 33. External Interrupt/Event GPIO Mapping
259
EXTI Registers
260
Interrupt Mask Register (EXTI_IMR)
260
Event Mask Register (EXTI_EMR)
260
Rising Trigger Selection Register (EXTI_RTSR)
260
Falling Trigger Selection Register (EXTI_FTSR)
261
Software Interrupt Event Register (EXTI_SWIER)
261
Pending Register (EXTI_PR)
262
EXTI Register Map
262
Table 47. External Interrupt/Event Controller Register Map and Reset Values
262
Analog-To-Digital Converter (ADC)
264
ADC Introduction
264
ADC Main Features
264
ADC Functional Description
264
Figure 34. Single ADC Block Diagram
265
ADC On-Off Control
266
ADC Clock
266
Channel Selection
266
Table 48. ADC Pins
266
Single Conversion Mode
267
Continuous Conversion Mode
267
Timing Diagram
268
Analog Watchdog
268
Figure 35. Timing Diagram
268
Scan Mode
269
Table 49. Analog Watchdog Channel Selection
269
Figure 36. Analog Watchdog's Guarded Area
269
Injected Channel Management
270
Figure 37. Injected Conversion Latency
270
Discontinuous Mode
271
Data Alignment
272
Channel-Wise Programmable Sampling Time
272
Figure 38. Right Alignment of 12-Bit Data
272
Figure 39. Left Alignment of 12-Bit Data
272
Figure 40. Left Alignment of 6-Bit Data
272
Conversion on External Trigger and Trigger Polarity
273
Table 50. Configuring the Trigger Polarity
273
Table 51. External Trigger for Regular Channels
274
Fast Conversion Mode
275
Table 52. External Trigger for Injected Channels
275
Data Management
276
Using the DMA
276
Managing a Sequence of Conversions Without Using the DMA
276
Conversions Without DMA and Without Overrun Detection
277
Multi ADC Mode
277
Figure 41. Multi ADC Block Diagram
278
Injected Simultaneous Mode
280
Regular Simultaneous Mode
281
Figure 42. Injected Simultaneous Mode on 4 Channels: Dual ADC Mode
281
Figure 43. Injected Simultaneous Mode on 4 Channels: Triple ADC Mode
281
Figure 44. Regular Simultaneous Mode on 16 Channels: Dual ADC Mode
282
Figure 45. Regular Simultaneous Mode on 16 Channels: Triple ADC Mode
282
Interleaved Mode
283
Figure 46. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Dual ADC Mode
283
Alternate Trigger Mode
284
Figure 47. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Triple ADC Mode
284
Figure 48. Alternate Trigger: Injected Group of each ADC
285
Combined Regular/Injected Simultaneous Mode
286
Figure 49. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Mode
286
Figure 50. Alternate Trigger: Injected Group of each ADC
286
Combined Regular Simultaneous + Alternate Trigger Mode
287
Figure 51. Alternate + Regular Simultaneous
287
Temperature Sensor
288
Figure 52. Case of Trigger Occurring During Injected Conversion
288
Figure 53. Temperature Sensor and VREFINT Channel Block Diagram
289
Battery Charge Monitoring
290
ADC Interrupts
290
Table 53. ADC Interrupts
290
ADC Registers
291
ADC Status Register (ADC_SR)
291
ADC Control Register 1 (ADC_CR1)
292
ADC Control Register 2 (ADC_CR2)
294
ADC Sample Time Register 1 (ADC_SMPR1)
297
ADC Sample Time Register 2 (ADC_SMPR2)
297
ADC Injected Channel Data Offset Register X (Adc_Jofrx)(X=1
298
ADC Watchdog Higher Threshold Register (ADC_HTR)
298
ADC Watchdog Lower Threshold Register (ADC_LTR)
298
ADC Regular Sequence Register 1 (ADC_SQR1)
299
ADC Regular Sequence Register 2 (ADC_SQR2)
299
ADC Regular Sequence Register 3 (ADC_SQR3)
300
ADC Injected Sequence Register (ADC_JSQR)
300
ADC Injected Data Register X (Adc_Jdrx) (X= 1
301
ADC Regular Data Register (ADC_DR)
301
ADC Common Status Register (ADC_CSR)
303
ADC Common Control Register (ADC_CCR)
304
11.13.17 ADC Common Regular Data Register for Dual and Triple Modes
307
(Adc_Cdr)
307
11.13.18 ADC Register Map
307
Table 54. ADC Global Register Map
307
Table 55. ADC Register Map and Reset Values for each ADC
308
Table 56. ADC Register Map and Reset Values (Common ADC Registers)
309
Digital-To-Analog Converter (DAC)
310
DAC Introduction
310
DAC Main Features
310
Table 57. DAC Pins
311
Figure 54. DAC Channel Block Diagram
311
DAC Functional Description
312
DAC Channel Enable
312
DAC Output Buffer Enable
312
DAC Data Format
312
Figure 55. Data Registers in Single DAC Channel Mode
312
DAC Conversion
313
Figure 56. Data Registers in Dual DAC Channel Mode
313
Figure 57. Timing Diagram for Conversion with Trigger Disabled TEN = 0
313
DAC Output Voltage
314
DAC Trigger Selection
314
DMA Request
314
Table 58. External Triggers
314
Noise Generation
315
Figure 58. DAC LFSR Register Calculation Algorithm
315
Triangle-Wave Generation
316
Figure 59. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
316
Figure 60. DAC Triangle Wave Generation
316
Dual DAC Channel Conversion
317
Independent Trigger Without Wave Generation
317
Figure 61. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
317
Independent Trigger with Single LFSR Generation
318
Independent Trigger with Different LFSR Generation
318
Independent Trigger with Single Triangle Generation
318
Independent Trigger with Different Triangle Generation
319
Simultaneous Software Start
319
Simultaneous Trigger Without Wave Generation
319
Simultaneous Trigger with Single LFSR Generation
320
Simultaneous Trigger with Different LFSR Generation
320
Simultaneous Trigger with Single Triangle Generation
320
Simultaneous Trigger with Different Triangle Generation
321
DAC Registers
321
DAC Control Register (DAC_CR)
321
DAC Software Trigger Register (DAC_SWTRIGR)
324
DAC Channel1 12-Bit Right-Aligned Data Holding Register
324
(Dac_Dhr12R1)
324
DAC Channel1 12-Bit Left Aligned Data Holding Register
325
(Dac_Dhr12L1)
325
DAC Channel1 8-Bit Right Aligned Data Holding Register
325
(Dac_Dhr8R1)
325
DAC Channel2 12-Bit Right Aligned Data Holding Register
325
(Dac_Dhr12R2)
325
DAC Channel2 12-Bit Left Aligned Data Holding Register
326
(Dac_Dhr12L2)
326
DAC Channel2 8-Bit Right-Aligned Data Holding Register
326
(Dac_Dhr8R2)
326
Dual DAC 12-Bit Right-Aligned Data Holding Register (DAC_DHR12RD)
326
DUAL DAC 12-Bit Left Aligned Data Holding Register
327
(Dac_Dhr12Ld)
327
DUAL DAC 8-Bit Right Aligned Data Holding Register
327
(Dac_Dhr8Rd)
327
DAC Channel1 Data Output Register (DAC_DOR1)
328
DAC Channel2 Data Output Register (DAC_DOR2)
328
DAC Status Register (DAC_SR)
328
DAC Register Map
329
Table 59. DAC Register Map
329
Digital Camera Interface (DCMI)
330
DCMI Introduction
330
DCMI Main Features
330
DCMI Pins
330
DCMI Clocks
330
Table 60. DCMI Pins
330
DCMI Functional Overview
331
Figure 62. DCMI Block Diagram
331
Figure 63. Top-Level Block Diagram
331
DMA Interface
332
DCMI Physical Interface
332
Table 61. DCMI Signals
332
Figure 64. DCMI Signal Waveforms
332
Table 62. Positioning of Captured Data Bytes in 32-Bit Words (8-Bit Width)
333
Table 63. Positioning of Captured Data Bytes in 32-Bit Words (10-Bit Width)
333
Table 64. Positioning of Captured Data Bytes in 32-Bit Words (12-Bit Width)
333
Synchronization
334
Table 65. Positioning of Captured Data Bytes in 32-Bit Words (14-Bit Width)
334
Figure 65. Timing Diagram
334
Capture Modes
336
Figure 66. Frame Capture Waveforms in Snapshot Mode
336
Crop Feature
337
Figure 67. Frame Capture Waveforms in Continuous Grab Mode
337
Figure 68. Coordinates and Size of the Window after Cropping
337
JPEG Format
338
Fifo
338
Figure 69. Data Capture Waveforms
338
Data Format Description
339
Data Formats
339
Monochrome Format
339
RGB Format
339
Table 66. Data Storage in Monochrome Progressive Video Format
339
Figure 70. Pixel Raster Scan Order
339
Ycbcr Format
340
DCMI Interrupts
340
Table 67. Data Storage in RGB Progressive Video Format
340
Table 68. Data Storage in Ycbcr Progressive Video Format
340
Table 69. DCMI Interrupts
340
DCMI Register Description
341
DCMI Control Register 1 (DCMI_CR)
341
DCMI Status Register (DCMI_SR)
343
DCMI Raw Interrupt Status Register (DCMI_RIS)
344
DCMI Interrupt Enable Register (DCMI_IER)
345
DCMI Masked Interrupt Status Register (DCMI_MIS)
346
DCMI Interrupt Clear Register (DCMI_ICR)
347
DCMI Embedded Synchronization Code Register (DCMI_ESCR)
347
DCMI Embedded Synchronization Unmask Register (DCMI_ESUR)
348
DCMI Crop Window Start (DCMI_CWSTRT)
350
DCMI Crop Window Size (DCMI_CWSIZE)
350
DCMI Data Register (DCMI_DR)
351
DCMI Register Map
351
Table 70. DCMI Register Map and Reset Values
351
Advanced-Control Timers (TIM1&TIM8)
353
TIM1&TIM8 Introduction
353
TIM1&TIM8 Main Features
353
Figure 71. Advanced-Control Timer Block Diagram
355
TIM1&TIM8 Functional Description
356
Time-Base Unit
356
Counter Modes
357
Figure 72. Counter Timing Diagram with Prescaler Division Change from 1 to 2
357
Figure 73. Counter Timing Diagram with Prescaler Division Change from 1 to 4
357
Figure 74. Counter Timing Diagram, Internal Clock Divided by 1
358
Figure 75. Counter Timing Diagram, Internal Clock Divided by 2
358
Figure 76. Counter Timing Diagram, Internal Clock Divided by 4
359
Figure 77. Counter Timing Diagram, Internal Clock Divided by N
359
Figure 78. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
359
Figure 79. Counter Timing Diagram, Update Event When ARPE=1
360
Figure 80. Counter Timing Diagram, Internal Clock Divided by 1
361
Figure 81. Counter Timing Diagram, Internal Clock Divided by 2
361
Figure 82. Counter Timing Diagram, Internal Clock Divided by 4
361
Figure 83. Counter Timing Diagram, Internal Clock Divided by N
362
Figure 84. Counter Timing Diagram, Update Event When Repetition Counter
362
Figure 85. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
363
Figure 86. Counter Timing Diagram, Internal Clock Divided by 2
364
Figure 87. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
364
Figure 88. Counter Timing Diagram, Internal Clock Divided by N
364
Repetition Counter
365
Figure 89. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
365
Figure 90. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
365
Figure 91. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
366
Clock Selection
367
Figure 92. Control Circuit in Normal Mode, Internal Clock Divided by 1
367
Figure 93. TI2 External Clock Connection Example
367
Figure 94. Control Circuit in External Clock Mode 1
368
Figure 95. External Trigger Input Block
369
Figure 96. Control Circuit in External Clock Mode 2
369
Capture/Compare Channels
370
Figure 97. Capture/Compare Channel (Example: Channel 1 Input Stage)
370
Figure 98. Capture/Compare Channel 1 Main Circuit
370
Input Capture Mode
371
Figure 99. Output Stage of Capture/Compare Channel (Channel 1 to 3)
371
Figure 100. Output Stage of Capture/Compare Channel (Channel 4)
371
PWM Input Mode
372
Forced Output Mode
373
Figure 101. PWM Input Mode Timing
373
Output Compare Mode
374
PWM Mode
375
Figure 102. Output Compare Mode, Toggle on OC1
375
Figure 103. Edge-Aligned PWM Waveforms (ARR=8)
376
Figure 104. Center-Aligned PWM Waveforms (ARR=8)
377
Complementary Outputs and Dead-Time Insertion
378
Figure 105. Complementary Output with Dead-Time Insertion
378
Figure 106. Dead-Time Waveforms with Delay Greater than the Negative Pulse
378
Using the Break Function
379
Figure 107. Dead-Time Waveforms with Delay Greater than the Positive Pulse
379
Figure 108. Output Behavior in Response to a Break
381
Clearing the Ocxref Signal on an External Event
382
Figure 109. Clearing Timx Ocxref
382
6-Step PWM Generation
383
Figure 110. 6-Step Generation, COM Example (OSSR=1)
383
One-Pulse Mode
384
Figure 111. Example of One Pulse Mode
384
Encoder Interface Mode
385
Table 71. Counting Direction Versus Encoder Signals
386
Figure 112. Example of Counter Operation in Encoder Interface Mode
387
Figure 113. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
387
Timer Input XOR Function
388
Interfacing with Hall Sensors
388
Figure 114. Example of Hall Sensor Interface
389
Timx and External Trigger Synchronization
390
Figure 115. Control Circuit in Reset Mode
390
Figure 116. Control Circuit in Gated Mode
391
Figure 117. Control Circuit in Trigger Mode
392
Timer Synchronization
393
Debug Mode
393
Figure 118. Control Circuit in External Clock Mode 2 + Trigger Mode
393
TIM1&TIM8 Registers
394
TIM1&TIM8 Control Register 1 (Timx_Cr1)
394
TIM1&TIM8 Control Register 2 (Timx_Cr2)
395
TIM1&TIM8 Slave Mode Control Register (Timx_Smcr)
398
TIM1&TIM8 Dma/Interrupt Enable Register (Timx_Dier)
400
Table 72. Timx Internal Trigger Connection
400
TIM1&TIM8 Status Register (Timx_Sr)
402
TIM1&TIM8 Event Generation Register (Timx_Egr)
403
TIM1&TIM8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
405
TIM1&TIM8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
408
TIM1&TIM8 Capture/Compare Enable Register (Timx_Ccer)
409
Table 73. Output Control Bits for Complementary Ocx and Ocxn Channels with
412
TIM1&TIM8 Counter (Timx_Cnt)
413
TIM1&TIM8 Prescaler (Timx_Psc)
413
TIM1&TIM8 Auto-Reload Register (Timx_Arr)
413
TIM1&TIM8 Repetition Counter Register (Timx_Rcr)
414
TIM1&TIM8 Capture/Compare Register 1 (Timx_Ccr1)
414
TIM1&TIM8 Capture/Compare Register 2 (Timx_Ccr2)
415
TIM1&TIM8 Capture/Compare Register 3 (Timx_Ccr3)
415
TIM1&TIM8 Capture/Compare Register 4 (Timx_Ccr4)
416
TIM1&TIM8 Break and Dead-Time Register (Timx_Bdtr)
416
TIM1&TIM8 DMA Control Register (Timx_Dcr)
418
TIM1&TIM8 DMA Address for Full Transfer (Timx_Dmar)
419
TIM1&TIM8 Register Map
420
Table 74. TIM1&TIM8 Register Map and Reset Values
420
General-Purpose Timers (TIM2 to TIM5)
422
TIM2 to TIM5 Introduction
422
TIM2 to TIM5 Main Features
422
TIM2 to TIM5 Functional Description
423
Time-Base Unit
423
Figure 119. General-Purpose Timer Block Diagram
423
Figure 120. Counter Timing Diagram with Prescaler Division Change from 1 to 2
424
Counter Modes
425
Figure 121. Counter Timing Diagram with Prescaler Division Change from 1 to 4
425
Figure 122. Counter Timing Diagram, Internal Clock Divided by 1
426
Figure 123. Counter Timing Diagram, Internal Clock Divided by 2
426
Figure 124. Counter Timing Diagram, Internal Clock Divided by 4
426
Figure 125. Counter Timing Diagram, Internal Clock Divided by N
427
Figure 126. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
427
Figure 127. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
428
Figure 128. Counter Timing Diagram, Internal Clock Divided by 1
429
Figure 129. Counter Timing Diagram, Internal Clock Divided by 2
429
Figure 130. Counter Timing Diagram, Internal Clock Divided by 4
429
Figure 131. Counter Timing Diagram, Internal Clock Divided by N
430
Figure 132. Counter Timing Diagram, Update Event
430
Figure 133. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
431
Figure 134. Counter Timing Diagram, Internal Clock Divided by 2
432
Figure 135. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
432
Figure 136. Counter Timing Diagram, Internal Clock Divided by N
432
Figure 137. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
433
Figure 138. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
433
Clock Selection
434
Figure 139. Control Circuit in Normal Mode, Internal Clock Divided by 1
434
Figure 140. TI2 External Clock Connection Example
435
Figure 141. Control Circuit in External Clock Mode 1
435
Capture/Compare Channels
436
Figure 142. External Trigger Input Block
436
Figure 143. Control Circuit in External Clock Mode 2
436
Figure 144. Capture/Compare Channel (Example: Channel 1 Input Stage)
437
Figure 145. Capture/Compare Channel 1 Main Circuit
437
Input Capture Mode
438
Figure 146. Output Stage of Capture/Compare Channel (Channel 1)
438
PWM Input Mode
439
Forced Output Mode
440
Figure 147. PWM Input Mode Timing
440
Output Compare Mode
441
PWM Mode
442
Figure 148. Output Compare Mode, Toggle on OC1
442
Figure 149. Edge-Aligned PWM Waveforms (ARR=8)
443
Figure 150. Center-Aligned PWM Waveforms (ARR=8)
444
One-Pulse Mode
445
Figure 151. Example of One-Pulse Mode
445
Clearing the Ocxref Signal on an External Event
446
Figure 152. Clearing Timx Ocxref
446
Encoder Interface Mode
447
Table 75. Counting Direction Versus Encoder Signals
447
Figure 153. Example of Counter Operation in Encoder Interface Mode
448
Figure 154. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
448
Timer Input XOR Function
449
Timers and External Trigger Synchronization
449
Figure 155. Control Circuit in Reset Mode
450
Figure 156. Control Circuit in Gated Mode
450
Figure 157. Control Circuit in Trigger Mode
451
Figure 158. Control Circuit in External Clock Mode 2 + Trigger Mode
452
Timer Synchronization
453
Figure 159. Master/Slave Timer Example
453
Figure 160. Gating Timer 2 with OC1REF of Timer 1
454
Figure 161. Gating Timer 2 with Enable of Timer 1
455
Figure 162. Triggering Timer 2 with Update of Timer 1
456
Figure 163. Triggering Timer 2 with Enable of Timer 1
456
Debug Mode
458
Figure 164. Triggering Timer 1 and 2 with Timer 1 TI1 Input
458
TIM2 to TIM5 Registers
459
Timx Control Register 1 (Timx_Cr1)
459
Timx Control Register 2 (Timx_Cr2)
461
Timx Slave Mode Control Register (Timx_Smcr)
462
Timx Dma/Interrupt Enable Register (Timx_Dier)
464
Table 76. Timx Internal Trigger Connection
464
Timx Status Register (Timx_Sr)
465
Timx Event Generation Register (Timx_Egr)
467
Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
468
Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
471
Timx Capture/Compare Enable Register (Timx_Ccer)
472
Table 77. Output Control Bit for Standard Ocx Channels
473
Timx Counter (Timx_Cnt)
474
Timx Prescaler (Timx_Psc)
474
Timx Auto-Reload Register (Timx_Arr)
474
Timx Capture/Compare Register 1 (Timx_Ccr1)
475
Timx Capture/Compare Register 2 (Timx_Ccr2)
475
Timx Capture/Compare Register 3 (Timx_Ccr3)
476
Timx Capture/Compare Register 4 (Timx_Ccr4)
476
Timx DMA Control Register (Timx_Dcr)
477
Timx DMA Address for Full Transfer (Timx_Dmar)
477
TIM2 Option Register (TIM2_OR)
479
TIM5 Option Register (TIM5_OR)
480
Timx Register Map
480
Table 78. TIM2 to TIM5 Register Map and Reset Values
480
General-Purpose Timers (TIM9 to TIM14)
482
TIM9 to TIM14 Introduction
482
TIM9 to TIM14 Main Features
482
TIM9/TIM12 Main Features
482
TIM10/TIM11 and TIM13/TIM14 Main Features
483
Figure 165. General-Purpose Timer Block Diagram (TIM9 and TIM12)
483
Figure 166. General-Purpose Timer Block Diagram (TIM10/11/13/14)
484
TIM9 to TIM14 Functional Description
485
Time-Base Unit
485
Counter Modes
486
Figure 167. Counter Timing Diagram with Prescaler Division Change from 1 to 2
486
Figure 168. Counter Timing Diagram with Prescaler Division Change from 1 to 4
486
Figure 169. Counter Timing Diagram, Internal Clock Divided by 1
487
Figure 170. Counter Timing Diagram, Internal Clock Divided by 2
487
Figure 171. Counter Timing Diagram, Internal Clock Divided by 4
488
Figure 172. Counter Timing Diagram, Internal Clock Divided by N
488
Clock Selection
489
Figure 175. Control Circuit in Normal Mode, Internal Clock Divided by 1
490
Figure 176. TI2 External Clock Connection Example
490
Capture/Compare Channels
491
Figure 177. Control Circuit in External Clock Mode 1
491
Figure 178. Capture/Compare Channel (Example: Channel 1 Input Stage)
491
Input Capture Mode
492
Figure 179. Capture/Compare Channel 1 Main Circuit
492
Figure 180. Output Stage of Capture/Compare Channel (Channel 1)
492
PWM Input Mode (Only for TIM9/12)
493
Forced Output Mode
494
Figure 181. PWM Input Mode Timing
494
Output Compare Mode
495
PWM Mode
496
Figure 182. Output Compare Mode, Toggle on OC1
496
One-Pulse Mode
497
Figure 183. Edge-Aligned PWM Waveforms (ARR=8)
497
Figure 184. Example of One Pulse Mode
497
TIM9/12 External Trigger Synchronization
498
Figure 185. Control Circuit in Reset Mode
499
Figure 186. Control Circuit in Gated Mode
500
Figure 187. Control Circuit in Trigger Mode
500
Timer Synchronization (TIM9/12)
501
Debug Mode
501
TIM9 and TIM12 Registers
502
TIM9/12 Control Register 1 (Timx_Cr1)
502
TIM9/12 Control Register 2 (Timx_Cr2)
503
TIM9/12 Slave Mode Control Register (Timx_Smcr)
504
Table 79. Timx Internal Trigger Connection
505
TIM9/12 Interrupt Enable Register (Timx_Dier)
506
TIM9/12 Status Register (Timx_Sr)
507
TIM9/12 Event Generation Register (Timx_Egr)
508
TIM9/12 Capture/Compare Mode Register 1 (Timx_Ccmr1)
509
TIM9/12 Capture/Compare Enable Register (Timx_Ccer)
512
TIM9/12 Counter (Timx_Cnt)
513
TIM9/12 Prescaler (Timx_Psc)
513
TIM9/12 Auto-Reload Register (Timx_Arr)
513
Table 80. Output Control Bit for Standard Ocx Channels
513
TIM9/12 Capture/Compare Register 1 (Timx_Ccr1)
514
TIM9/12 Capture/Compare Register 2 (Timx_Ccr2)
514
TIM9/12 Register Map
514
Table 81. TIM9/12 Register Map and Reset Values
514
TIM10/11/13/14 Registers
516
TIM10/11/13/14 Control Register 1 (Timx_Cr1)
516
TIM10/11/13/14 Status Register (Timx_Sr)
516
TIM10/11/13/14 Event Generation Register (Timx_Egr)
517
TIM10/11/13/14 Capture/Compare Mode Register 1
519
(Timx_Ccmr1)
519
TIM10/11/13/14 Capture/Compare Enable Register
521
(Timx_Ccer)
521
Table 82. Output Control Bit for Standard Ocx Channels
521
TIM10/11/13/14 Counter (Timx_Cnt)
522
TIM10/11/13/14 Prescaler (Timx_Psc)
522
TIM10/11/13/14 Auto-Reload Register (Timx_Arr)
522
TIM10/11/13/14 Capture/Compare Register 1 (Timx_Ccr1)
523
TIM11 Option Register 1 (TIM11_OR)
523
TIM10/11/13/14 Register Map
524
Table 83. TIM10/11/13/14 Register Map and Reset Values
524
Basic Timers (TIM6&TIM7)
525
TIM6&TIM7 Introduction
525
TIM6&TIM7 Main Features
525
Figure 188. Basic Timer Block Diagram
525
TIM6&TIM7 Functional Description
526
Time-Base Unit
526
Counting Mode
527
Figure 189. Counter Timing Diagram with Prescaler Division Change from 1 to 2
527
Figure 190. Counter Timing Diagram with Prescaler Division Change from 1 to 4
527
Figure 191. Counter Timing Diagram, Internal Clock Divided by 1
528
Figure 192. Counter Timing Diagram, Internal Clock Divided by 2
528
Figure 193. Counter Timing Diagram, Internal Clock Divided by 4
529
Figure 194. Counter Timing Diagram, Internal Clock Divided by N
529
Clock Source
530
Debug Mode
530
TIM6&TIM7 Registers
531
TIM6&TIM7 Control Register 1 (Timx_Cr1)
531
TIM6&TIM7 Control Register 2 (Timx_Cr2)
532
TIM6&TIM7 Dma/Interrupt Enable Register (Timx_Dier)
532
TIM6&TIM7 Status Register (Timx_Sr)
533
TIM6&TIM7 Event Generation Register (Timx_Egr)
533
TIM6&TIM7 Counter (Timx_Cnt)
533
TIM6&TIM7 Prescaler (Timx_Psc)
534
TIM6&TIM7 Auto-Reload Register (Timx_Arr)
534
TIM6&TIM7 Register Map
535
Table 84. TIM6&TIM7 Register Map and Reset Values
535
Independent Watchdog (IWDG)
536
IWDG Introduction
536
IWDG Main Features
536
IWDG Functional Description
536
Hardware Watchdog
536
Register Access Protection
536
Debug Mode
537
IWDG Registers
537
Table 85. Min/Max IWDG Timeout Period at 32 Khz (LSI)
537
Figure 198. Independent Watchdog Block Diagram
537
Key Register (IWDG_KR)
538
Prescaler Register (IWDG_PR)
539
Reload Register (IWDG_RLR)
539
Status Register (IWDG_SR)
540
IWDG Register Map
540
Table 86. IWDG Register Map and Reset Values
540
Window Watchdog (WWDG)
541
WWDG Introduction
541
WWDG Main Features
541
WWDG Functional Description
541
Figure 199. Watchdog Block Diagram
542
How to Program the Watchdog Timeout
543
Figure 200. Window Watchdog Timing Diagram
543
Debug Mode
544
Table 87. Timeout Values at 30 Mhz (F PCLK1 )
544
WWDG Registers
545
Control Register (WWDG_CR)
545
Configuration Register (WWDG_CFR)
546
Status Register (WWDG_SR)
546
WWDG Register Map
547
Table 88. WWDG Register Map and Reset Values
547
Cryptographic Processor (CRYP)
548
CRYP Introduction
548
CRYP Main Features
548
Table 89. Number of Cycles Required to Process each 128-Bit Block (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
548
Table 90. Number of Cycles Required to Process each 128-Bit Block (Stm32F42Xxx and Stm32F43Xxx)
548
CRYP Functional Description
550
Figure 201. Block Diagram (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
550
DES/TDES Cryptographic Core
551
Figure 202. Block Diagram (Stm32F42Xxx and Stm32F43Xxx)
551
Figure 203. DES/TDES-ECB Mode Encryption
553
Figure 204. DES/TDES-ECB Mode Decryption
553
Figure 205. DES/TDES-CBC Mode Encryption
555
AES Cryptographic Core
556
Figure 206. DES/TDES-CBC Mode Decryption
556
Figure 207. AES-ECB Mode Encryption
557
Figure 208. AES-ECB Mode Decryption
558
Figure 209. AES-CBC Mode Encryption
559
Figure 210. AES-CBC Mode Decryption
560
Figure 211. AES-CTR Mode Encryption
561
Figure 212. AES-CTR Mode Decryption
562
Figure 213. Initial Counter Block Structure for the Counter Mode
562
Data Type
567
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ST STM32F40 Series Programming Manual (29 pages)
Brand:
ST
| Category:
Microcontrollers
| Size: 0.39 MB
Table of Contents
Table 1. Applicable Products
1
Table of Contents
2
Glossary
5
Flash Memory Interface
6
Introduction
6
Main Features
6
Flash Memory
7
Table 2. Flash Module Organization
7
Read Interface
8
Relation between CPU Clock Frequency and Flash Memory Read Time
8
Table 3. Number of Wait States According to CPU Clock (HCLK) Frequency
8
Adaptive Real-Time Memory Accelerator (ART Accelerator™)
9
Figure 2. Sequential 32-Bit Instruction Execution
10
Erase and Program Operations
11
Unlocking the Flash Control Register
11
Program/Erase Parallelism
12
Erase
12
Table 4. Program/Erase Parallelism
12
Programming
13
Interrupts
14
Option Bytes
14
Description of User Option Bytes
14
Table 5. Flash Interrupt Requests
14
Table 6. Option Byte Organization
14
Programming User Option Bytes
15
Table 7. Description of the Option Bytes
15
Read Protection (RDP)
16
Table 8. Access Versus Read Protection Level
17
Write Protections
18
One-Time Programmable Bytes
19
Table 9. OTP Part Organization
19
Flash Interface Registers
20
Flash Access Control Register (FLASH_ACR)
20
Flash Key Register (FLASH_KEYR)
21
Flash Option Key Register (FLASH_OPTKEYR)
21
Flash Status Register (FLASH_SR)
22
Flash Control Register (FLASH_CR)
23
Flash Option Control Register (FLASH_OPTCR)
24
Flash Interface Register Map
26
Table 10. Flash Register Map and Reset Values
26
Revision History
27
Table 11. Document Revision History
27
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