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RM0351
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.
Bits 3:0 Reserved, must be kept at reset value.
17.5.5
DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel1.
17.5.6
DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
These bits are written by software which specifies 12-bit data for DAC channel2.
27
26
25
Res.
Res.
Res.
11
10
9
DACC1DHR[11:0]
rw
rw
rw
rw
27
26
25
Res.
Res.
Res.
11
10
9
Res.
Res.
Res.
27
26
25
Res.
Res.
Res.
11
10
9
rw
rw
rw
24
23
22
Res.
Res.
Res.
8
7
6
rw
rw
rw
24
23
22
Res.
Res.
Res.
8
7
6
Res.
rw
rw
24
23
22
Res.
Res.
Res.
8
7
6
DACC2DHR[11:0]
rw
rw
rw
DocID024597 Rev 3
Digital-to-analog converter (DAC)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
rw
rw
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
DACC1DHR[7:0]
rw
rw
rw
rw
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
rw
rw
rw
rw
17
16
Res.
Res.
1
0
Res.
Res.
17
16
Res.
Res.
1
0
rw
rw
17
16
Res.
Res.
1
0
rw
rw
563/1693
573
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