ST STM32L4x6 Reference Manual page 687

RM0351
Bit 2 UDR: Update display request
Each time software modifies the LCD_RAM it must set the UDR bit to transfer the updated
data to the second level buffer. The UDR bit stays set until the end of the update and during
this time the LCD_RAM is write protected.
Note: When the display is disabled, the update is performed for all LCD_DISPLAY locations.
Note: Writing 0 on this bit or writing 1 when it is already 1 has no effect. This bit can be
Bit 1 SOF: Start of frame flag
This bit is set by hardware at the beginning of a new frame, at the same time as the display
data is updated. It is cleared by writing a 1 to the SOFC bit in the LCD_CLR register. The bit
clear has priority over the set.
ENS: LCD enabled status
This bit is set and cleared by hardware. It indicates the LCD controller status.
Note: The ENS bit is set immediately when the LCDEN bit in the LCD_CR goes from 0 to 1.
0: No effect
1: Update Display request
When the display is enabled, the update is performed only for locations for which
commons are active (depending on DUTY). For example if DUTY = 1/2, only the
LCD_DISPLAY of COM0 and COM1 will be updated.
cleared by hardware only. It can be cleared only when LCDEN = 1
0: No event
1: Start of Frame event occurred. An LCD Start of Frame Interrupt is generated if the SOFIE
bit is set.
0: LCD Controller disabled.
1: LCD Controller enabled
On deactivation it reflects the real status of LCD so it becomes 0 at the end of the last
displayed frame.
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Liquid crystal display controller (LCD)
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