Short-Circuit Detector - ST STM32L4x6 Reference Manual

Digital filter for sigma delta modulators (DFSDM)
cannot be used for analog watchdog feature at this input clock speed. Therefore user must
properly configure the number of watched channels and analog watchdog filter parameters
with respect to input sampling clock speed and DFSDM frequency.
Analog watchdog filter data for given channel y is available for reading by firmware on field
WDATA[15:0] in DFSDM_CHWDATyR register. That analog watchdog filter data is
converted continuously (if CHEN=1 in DFSDM_CHCFGyR1 register) with the data rate
given by the analog watchdog filter setting and the channel input clock frequency.
The analog watchdog filter conversion works like a regular Fast Continuous Conversion
without the intergator. The number of serial samples needed for one result from analog
watchdog filter output (at channel input clock frequency f
first conversion:
for Sinc
for FastSinc filter: number of samples = [F
next conversions:
for Sinc
where:
F ....... filter oversampling ratio: F
OSR
register)
F ....... the filter order: F
ORD
In case of output data register monitoring (AWFSEL=0), the comparison is done after an
offset correction and a right bit shift of final data (see OFFSET[23:0] and DTRBS[4:0] fields
in DFSDM_CHCFGyR2 register). A comparison is performed after each injected or regular
end of conversion for the channels selected by AWDCH[7:0] field (in DFSDMx_CR2
register).
The status of an analog watchdog event is signalized in DFSDMx_AWSR register where a
given event is latched. AWHTF[y]=1 flag signalizes crossing AWHT[23:0] value on channel
y. AWLTF[y]=1 flag signalizes crossing AWLT[23:0] value on channel y. Latched events in
DFSDMx_AWSR register are cleared by writing '1' into the corresponding clearing bit
CLRAWHTF[y] or CLRAWLTF[y] in DFSDMx_AWCFR register.
The global status of an analog watchdog is signalized by the AWDF flag bit in DFSDMx_ISR
register (it is used for the fast detection of an interrupt source). AWDF=1 signalizes that at
least one watchdog occurred (AWHTF[y]=1 or AWLTF[y]=1 for at least one channel). AWDF
bit is cleared when all AWHTF[7:0] and AWLTF[7:0] are cleared.
An analog watchdog event can be assigned to break output signal. There are four break
outputs to be assigned to a high or low threshold crossing event (
break signal assignment to a given analog watchdog event is done by BKAWH[3:0] and
BKAWL[3:0] fields in DFSDMx_AWHTR and DFSDMx_AWLTR register.
21.3.11

Short-circuit detector

The purpose of a short-circuit detector is to signalize with a very fast response time if an
analog signal reached saturated values (out of full scale ranges) and remained on this value
given time. This behavior can detect short-circuit or open circuit errors (e.g. overcurrent or
overvoltage). An interrupt/event/break generation can be invoked.
Input data into a short-circuit detector is taken from channel transceiver outputs.
622/1693
x
filters (x=1..5): number of samples = [F
x
and FastSinc filters: number of samples = [FOSR * IOSR]
= AWFORD[1:0] (see DFSDM_AWSCDyR register)
ORD
DocID024597 Rev 3
DFSDM_CKIN
* F
OSR
* 4 + 2 + 1]
OSR
= AWFOSR[4:0]+1 (see DFSDM_AWSCDyR
OSR
):
+ F + 1]
ORD ORD
DFSDM_BREAK[3:0]
RM0351
). The