Starting Conversions (Adstart, Jadstart) - ST STM32L4x6 Reference Manual

RM0351
16.3.15

Starting conversions (ADSTART, JADSTART)

Software starts ADC regular conversions by setting ADSTART=1.
When ADSTART is set, the conversion starts:
• Immediately: if EXTEN = 0x0 (software trigger)
•
At the next active edge of the selected regular hardware trigger: if EXTEN /= 0x0
Software starts ADC injected conversions by setting JADSTART=1.
When JADSTART is set, the conversion starts:
•
Immediately, if JEXTEN = 0x0 (software trigger)
• At the next active edge of the selected injected hardware trigger: if JEXTEN /= 0x0
Note: In auto-injection mode (JAUTO=1), use ADSTART bit to start the regular conversions
followed by the auto-injected conversions (JADSTART must be kept cleared).
ADSTART and JADSTART also provide information on whether any ADC operation is
currently ongoing. It is possible to re-configure the ADC while ADSTART=0 and
JADSTART=0 are both true, indicating that the ADC is idle.
ADSTART is cleared by hardware:
•
In single mode with software regular trigger (CONT=0, EXTSEL=0x0)
–
•
In all cases (CONT=x, EXTSEL=x)
–
Note: In continuous mode (CONT=1), ADSTART is not cleared by hardware with the assertion of
EOS because the sequence is automatically relaunched.
When a hardware trigger is selected in single mode (CONT=0 and EXTSEL /=0x00),
ADSTART is not cleared by hardware with the assertion of EOS to help the software which
does not need to reset ADSTART again for the next hardware trigger event. This ensures
that no further hardware triggers are missed.
JADSTART is cleared by hardware:
•
in single mode with software injected trigger (JEXTSEL=0x0)
–
•
in all cases (JEXTSEL=x)
–
16.3.16 Timing
The elapsed time between the start of a conversion and the end of conversion is the sum of
the configured sampling time plus the successive approximation time depending on data
resolution:
T
CONV
T
CONV
at any end of regular conversion sequence (EOS assertion) or at any end of sub-
group processing if DISCEN = 1
after execution of the ADSTP procedure asserted by the software.
at any end of injected conversion sequence (JEOS assertion) or at any end of
sub-group processing if JDISCEN = 1
after execution of the JADSTP procedure asserted by the software.
= T + T = [ 2.5
SMPL SAR
= T + T = 31.25 ns
SMPL SAR
DocID024597 Rev 3
+ 12.5 ] x T
|min |12bit ADC_CLK
+ 156.25 ns
|min |12bit
Analog-to-digital converters (ADC)
= 187.5 ns (for F
ADC_CLK
= 80 MHz)
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